First of two parts: Cost and supply chain issues remain as advanced packaging begins to ramp.
Semiconductor Engineering sat to discuss advanced packaging issues with Juan Rey, senior director of engineering for Calibre at Mentor Graphics; Max Min, senior technical manager at Samsung; and Lisa Minwell, eSilicon’s senior director of IP marketing. What follows are excerpts of that conversation.
SE: Now that we’re seeing real 2.5D and fan-out designs, what kinds of problems are showing up?
Minwell: There were quite a number of problems that we expected to occur, particularly with the supply chain and different kinds of interposers—whether those are organic or silicon. Working with that has taken from 2011 until today. We’re finally getting that into production.
Min: My focus is 2.5D. We started a couple years ago with chip-to-chip, not chip-to-HBM. Still, we had some experience with this and we are not seeing any major technical problems. We are trying to get to 100% yield, but there are still some minor issues to solve. And some people are still not ready for high-volume products.
Rey: One of the issues with the supply chain involves the way companies communicate. Some of them are used to having very well defined PDKs for new technology. When you have to merge two communities—the packaging community with the design community—you start seeing some differences. The IC designers are used to a certain methodology, and that isn’t exactly the same as the packaging community. The packaging community is used to having a little more flexibility. We’re trying to talk about co-design of chip and package. At that point, the design engineers used to give their information to the package engineers, and they expect them to deliver the package. It was a waterfall methodology. If you have to work with a foundry, the communication and methodology already exists. With the packaging houses, it does not. We’re seeing a need for rapid maturity in that relationship. It has to benefit designers. The designers are used to following a methodology. This needs to extend what they’re doing now with rules and PDKs.
Minwell: The whole concept of interposer design itself needs work, from the power integrity analysis to the signal integrity analysis. That’s the learning curve people are on right now. They’re also trying to do more than just connect to external memory. It’s also a chip-to-chip connection. They’re trying to figure out what type of IP to use—combo PHY IP that can be configured to communicate to an external memory stack or to another chip. We’re wrestling with that right now.
SE: What tradeoffs are involved there?
Minwell: The goal is to have higher bandwidth and lower power, rather than two packaged chips on a board with the latency between them. They’re trying to pack more bandwidth into one package and reduce the latency. Also, they want to have this application-specific product where it can plug and play, whether it has a DRAM stack in there or not. If they’re fearful about the cost of the DRAM stack, they may have a low-cost product as well as a higher-cost product where they pull in the DRAM.
Min: The issue is external memory versus internal memory. External memory requires a very large driver to drive a large amount of data all the way to an external interface. That requires a larger chip size, especially for the chip to I/O. The I/O itself is very small, but the signal has to travel a very long way. With a 2.5D interposer this is a silicon process, but a silicon interposer is still very large. You have a large R but a small c. Because of that you have a performance degradation. A lot of people play around with those numbers because they can’t play around with the thickness. The thickness is part of the PDK. It’s how we’re going to make the dielectric with the metal. We let them know the design rules. Then the customer will tell us what they want—copper, wider, metal layers, or whatever they want to do.
Rey: Some of those technologies are coming to maturity and are very well defined, and some are in very well defined niches. But these are still not mature processes. So we find ourselves doing a lot of research in order to figure out what can go wrong. Parasitic effects are at the center of some of the things we are doing. The capacitance is going to be at the coupling for the interposer and the chip. Typically, we do a lot of advance activities in this area. We are still doing research here.
SE: All of these problems are an indication that progress is being made on the technology. But how do we cut the costs of the interposer, the design and the entire package?
Minwell: Right now, if you take a look at the cost of the interposer for a high-end system, it’s not a big deal. It’s 20% or less of the total chip. But it is an added cost for the interposer and for assembly. When you look at smaller chips, as we progress to more consumer applications, this is way too costly. There are several suppliers working on new technologies.
SE: Such as organic interposers?
Minwell: Yes, as well as fan-out wafer-level packaging. There have been a lot of studies recently. This has promise. One of the things that is troubling us is the availability of IP—especially analog and SerDes IP. It’s a lot of effort to be able to move that IP from one technology node to the next. When it’s fully verified at 28nm, just being able to use that IP as a tile at 28nm would be ideal. It would solve a lot of IP availability issues.
SE: But if you look at all of the implementations of 2.5D and fan-outs so far, though, all of the IP, memory and logic have all been from the same process node.
Minwell: That’s true. But we feel that if we can get all of the packaging and materials, the cost would be at a price point that would make tiles a possibility. But that brings up a whole other issue. How do you market tiles? Who’s going to market and sell those tiles and characterize them? Now you’ve moved your level of abstraction up. Rather than porting it to a technology node and having to go to all the EDA tools to validate it, now you have a known good die. You’ve moved up the level of abstraction, but there is nothing in place to take care of that.
Min: A silicon interposer in a package is expensive. We are looking at removing the silicon interposer and using other technologies. One approach is fan-out wafer-level packaging. There is also 2.1D with an organic substrate. We would still have a known good die with the substrate. But the technology itself is still under development. We are still working on 2.1D and fan-out wafer-level packaging.
Rey: From our perspective, we need to be ready to help with the tool set. We have been looking ahead in these directions through larger research projects. We have been working with Leti in France, where the whole idea is to look into different types of silicon interposers and Wide I/O and active interposers, where several elements are placed inside the interposer. We will continue working with them on other more exotic types of projects. Very likely that will extend to silicon photonics. We want to facilitate the flow, and they are trying to understand where tools like physical verification can be extended. So our focus is how to extend technology without increasing the cost.
Advanced Packaging Options, Issues
New fan-out technology under development; 2.5D trouble spots come into focus.
2.5D Becomes A Reality
Experts at the table, part 1: Lower power, better bandwidth and smaller form factor propel advanced packaging into commercial use; cost is still rather murky.
2.5D Becomes A Reality Part 2
Experts at the table, part 2: Does putting chips together in a package really cut time to market?
Thinking Outside The Chip
Intel joins AMD, IBM on advanced packaging; performance is the key driver.
Packaging Wars Begin
OSATs and foundries begin to ramp offerings and investments in preparation for mainstream multi-chip architectures.