Technology challenges will be solved faster than the business model.
By Barbara Jorgensen and Ed Sperling
Stacked die, which promise high levels of integration, a tiny footprint, energy conservation and blinding speed, still have some big hurdles to overcome.
Cost, packaging and manufacturability continue to make steady progress, with test chips being produced by all of the major foundries. But in a disaggregated ecosystem, the supply chain remains a big sticking point.
“There are a number of issues 3D is struggling with today, but the one that’s not really ready is the business model,” said Herb Reiter, president of EDA2ASIC Consulting. “Of course, the supply chain starts with the customer, who want as much functionality packed on the smallest space possible using the least amount of power. And they want this with absolute reliability and almost for free.”
Technology-wise, the industry’s wish list for stacked die 3D-IC includes materials that enable thinner and sturdier wafers; solders with more flexible melting and bonding properties; solutions for heat-dissipation and non-invasive testing.
“The technology issues will be solved before the business model/supply chain [issues],” said Kurt Shuler, vice president of marketing at Arteris.
The semiconductor supply chain consists of numerous highly specialized companies that excel at their chosen discipline: EDA, IP, fabs/foundries, design, packaging and test. In the standard process of chip making, the elements of the design and then the chip itself are passed relatively seamlessly from one company to another. With stacked die, that’s not so simple to do—or even to define the boundaries of who does what.
Stacked die even have raised the issue about just how disaggregated the supply chain can be. While foundries such as GlobalFoundries, TSMC and UMC all are offering interposers based on highly restrictive design rules, there also is research underway for glass and organic interposers, including silicon on insulator. The advantage of the organic approach is that it is softer, which eases concerns about the thermal expansion coefficient of the interposer material compared with silicon.
Also new to the mix is high-bandwidth memory, which is just entering sampling now, with volume production expected in Q1 of 2014. Considering there is no DDR5 planned, this is considered the likely successor to DDR4 memory. And coupled with improvements in yield, testability and manufacturability, stacked die will be at least technically feasible in the very near future. After that, it’s largely a supply chain problem.
“The big questions are who will manufacture these chips and what standards will be in place,” said Javier DeLaCruz, senior director of engineering at eSilicon. “Which supply chain path will dominate is a very complex issue. If there is any indecision, people will stay on the sidelines. That’s why we’re picking who we think the leaders should be right now. That also depends on whether these are homogeneous versus heterogeneous die. If it’s homogeneous, it never leaves the foundry. It it’s heterogeneous, it’s an OSAT issue. They have to deal with handling of a thinner wafer. That’s why we’re developing a process so you never have to handle a thinned wafer. You bond it to another chip or use a temporary carrier, which can be blank silicon or glass.”
Still, there is an upside to this approach that warrants the effort—as well as a feeling that inevitably this is the path the industry will ultimately have to take, DeLaCruz said. “Right now you can route to off-chip memory, and in the networking world there are boards with 36 layers to access lots of memory. But if memories disappear on the ASIC and the number of balls decrease and the only thing left is SerDes, then the bottleneck of pins in the package goes away.”
That also streamlines the IP interconnect issue, which has been a growing concern given the increasing amount of IP—both commercially and internally developed—that is being included in SoCs. “Customers designing SoCs find that doing their own interconnect is getting too cumbersome and complex due to the large number of IP blocks they need to integrate into their system,” said Frank Ferro, director of product marketing for system IP developer Sonics.
A stacked die alleviates some of that concern, as well as another big concern for the supply chain—not all of the IP needs to be developed using the same process technology. That’s particularly important for analog IP, which is difficult to shrink to advanced manufacturing processes.
Who does what
Stacked die also raises questions about who does what in the supply chain as well as ownership issues in case something doesn’t work. This is the known-good-die issue, and while it has received a lot of attention it has never been resolved.
“If you have a product on a single die, it becomes pretty clear who owns that,” says Shuler. “When you get to 3D, with through-silicon vias (TSVs) and Wide I/O memory and you build it on a single chip, it gets complicated. Who is responsible for what at what stage of development?
He noted that reverse engineering a chip that doesn’t work coming out of the fab doesn’t necessarily get to the root cause of the problem in a stacked die. “Determining responsibility, whether it’s for financial or design reasons, [in 3D IC] is hard to get right,” he said.
When the industry moves to 3D, the supply chain has a lot of conflict built in, noted Reiter. “Let’s say you have a CPU and a memory stack on one interposer, and this configuration sells for $20. The customer has to buy the CPU and memory stack from somewhere, and the question becomes how to distribute the money. Half and half? Sixty-forty? One company could say, ‘My contribution is worth more so I want a bigger piece of the end sales price.’ The biggest challenge for 3D these days is everybody needs to invest—their own engineers and equipment—and this costs money.”
With 3D integration, Reiter said, wafer fabs will have to cooperate vertically as well as horizontally within the 3D-IC ecosystem. For example, they’ll need to agree horizontally on interconnect standards to enable vertical stacking of die from different fabs in one package. For cost-effective vertical cooperation, fabs need to agree with OSATs on hand-off criteria in the manufacturing flow—namely who is responsible for wafer thinning and TSV reveal, redistribution layer and test, among other things.
Test is another issue, and all of the big EDA vendors have been working to solve this problem because probes could damage multiple chips in a package. The end-to-end investment in 3D-compatible equipment is significant. And even then, it’s uncertain if all the problems will show up.
Sometimes a large customer can force alignment in the supply chain by demanding new technology. Wal-Mart accomplished this when it asked it suppliers to use RFID tags on all retail items. In 3D, the customer faces a lot of risk. “The end customer is a huge force, but every new technology is more expensive than older technology and until volume and yields are reached price remains at a premium,” said Reiter. “There’s also the risk the new technology won’t resonate—that is particularly risky in the consumer market. 3D IC has a compelling value in, for example, the satellite market, where size and weight are everything and the end-product costs millions of dollars. It’s not the same with cellphones because the cost disadvantage will make the end product unattractive. “
Another way to encourage cooperation is a consortium or industry association. “Associations have a difficult role because they have a common cause, but their members are also businesses that have their own—and shareholder—interests at heart,” said Reiter. “This is a very delicate area, especially because today these 2.5 and 3D chips are a very small part of [chip company] revenue and profits.” Management may have a hard time justifying investment in further 3D development.”