3D Integration

By Katherine Derbyshire

It’s a central problem of integrated circuit scaling. While transistor delay goes down along with channel length, interconnect delay goes up. The 90 nm technology node featured a transistor delay of about 1.6 ps, while a 1 mm long interconnect wire added about 5×10² ps. For the 22 nm node, the ITRS estimates transistor delay at 0.4 ps, but interconnect delay at about 1×10⁴ ps.

Smaller transistors are faster, while interconnect resistance goes up as the cross section of the line goes down. Surface scattering, grain boundary scattering, and the higher resistance of the diffusion barrier all contribute to RC delay. Reduced interconnect length is often offered as a benefit of 3-D integration, but it’s important to consider whether we have reduced the length of board-level, or circuit-level interconnects.

3-D integration with through-silicon vias (TSVs) primarily affects the interconnects between chips, and therefore reduces the amount of circuit board area. As usually implemented, this approach stacks several memory or other chips vertically, landing TSVs on the upper chip onto conventional bond pads on the lower chip. Each chip within the stack represents a complete 2-D design, with all of its circuit-level interconnections.

In contrast, MonolithIC 3D proposes true 3-D design integration, in which the layers of a stack are designed as a single unit. Partitioning the design appropriately allows global interconnects to be vertical as well as horizontal, with shorter wires. Less area is needed for repeaters and similar elements; the total silicon area is lower. As Lili Zhou and co-workers at the University of Washington showed (ICCD 2007), multi-layer design can cut silicon area in half and total interconnect length by two-thirds.

The MonolithIC 3D approach depends on layer transfer technology — similar to that used in Soitec’s silicon-on-insulator wafers — to stack thin silicon device layers. Because the vias in such a structure only need to pass through the active layer, they can be much smaller than conventional TSVs, with dimensions only 3x larger than the top interconnect layer. The company claims that, for many applications, their approach provides a scaling benefit equivalent to one process node, without the extraordinary process and equipment costs. It’s an intriguing possibility, but hard to evaluate until it’s been realized in silicon.