How CMP affects mixed-signal layouts and what to watch out for.
With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to have issues both in delivering the required layer densities, and with flexibility in maintaining symmetry for device matching. This paper describes a novel approach in which the dummy patterns can be easily customised and controlled from a design entry system, and used to drive a Tcl-programmable Calibre SmartFill engine to allow the flexibility required to add dummy fill to a variety of analog layout styles.
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