Accelerating Design-For-Test Pattern Simulation

Combining DFT with emulation to speed time to market and increase yield.


The Veloce DFT App presents a true “left shift” improvement for a traditional chip design schedule that requires comprehensive gate-level simulations to develop ATPG, BIST, or functional patterns. It enables running complete patterns for DFT verification in a reasonable time to shorten the pattern development cycle. The Veloce DFT App fits seamlessly into the Veloce ecosystem, enabling a host of other powerful apps and features in the context of DFT infrastructure validation. The high performance of emulation adds more “simulation cycles,” pulling the DFT schedule to within the time the project management has allocated. This means quicker time-to-market and increased yield, which means higher profits.

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