Advanced Lithography: Moore’s Law Moves On

If designers can stand all the rules that come with quadruple patterning, the road is clear to 10nm and maybe beyond.

popularity

Every February, experts in nano patterning technologies converge in San Jose, Calif., to present their road maps, brainstorms and results at the SPIE Advanced Lithography Symposium. This year, there was more confusion than ever, partly the result of sessions in unlabeled (but beautiful) new ballrooms at the Convention Center, but mostly because of industry divergences.

There is no longer a single preferred lithography strategy or method, nor assurance that mere scaling will result in lower cost and better performance. However, it was clear that some of the industry had plans to build “7nm node” chips with ~40nm contacted pitches whether or not the long-delayed EUV exposure technology was available. Just how to do it was obscure enough to be argued by a “court” one evening. Contenders included imprint, directed self assembly, complex deposition and etch (MPT) schemes and the perennial also-ran: direct write e-beam. Other industry segments were being forced into the third dimension by device physics or marketplace realities.

Still, the overall message of the meeting was that there had been no breakthroughs during the previous year, just marginal progress, but that was enough. The long-awaited first EUVL production results with the ASML NXE: 3300 tool at TSMC were delayed by a laser malfunction. They had achieved 10W of source power using 20% of the tin droplets. Turning up the laser duty factor to blast all 100% should have achieved the 50W target, but….unfortunately, during the low-power exposures, a bit of dust fell on the reticle surface, resulting in a new repeating defect, according to Jack Chen of TSMC.

That one wafer illustrated the need for EUV pellicles in addition to some means to find and hide — or correct — 2nm to 3nm mask phase defects. So, more innovations are needed before EUVL can be used in high-volume production. If they came in time for the 11nm node, Chen predicted that 13.5nm EUVL would have to be used in a double patterning mode anyway!

On the other hand, Mark Phillips of Intel foresaw EUVL being inserted to expose the cut mask and vias in a complementary lithography strategy where the line gratings were made using 193i extensions. Because the bright areas of such a mask cover a small fraction of the area, substrate phase defects can easily be hidden under opaque material. Attempting to fabricate the cuts and vias with 193i multi-patterning would require 9 masks for one ~12nm level, according to Phillips.

Grating-based structures constituted one continuing theme of the conference. Whether it was 100nm grating, printed by the roll for wire grid polarizers using step and flash imprint or self aligned quadruple patterning (SAQP) at 193nm for memory, or real ARM logic interconnect levels, everything seemed to be devolving towards gratings. The challenge for semiconductor applications continued to be the cut masks and vias. When the gratings on orthogonal layers have the same pitch, the via dimension must be near the half pitch, which is not easy with SAQP. Implementing larger vias either means blocking 3 adjacent lines (to obey SAQP coloring rules) or having larger traces.

Kenichi Oyama of TEL described a variety of hole-shrink methods that can yield the structures needed for vias and line cutting. Plasma assisted polymer deposition reduced photoresist hole sizes to 23nm while an RIE hole shrink method trimmed openings in a photoresist to 19nm in a SiO² layer beneath an SOC spacer — while separating holes that appeared to have overlapped prior to etch! With two such layers, line-cut slots could be made down to 14nm width while contact holes reached 16nm. All that would be needed then to get to ~5nm half pitch chips was a 5.5nm grating, also fabricated by TEL using ArF exposure, CVD carbon spacers and SA8P – self aligned octuple patterning!

Making circuit structures 35 (or 27 or 19) times smaller than the 193nm exposure wavelength requires extraordinary precision from the first exposure process. Even a 1nm error in CD or overlay of the original resist pattern propagates into unacceptable distortions in 7nm multipatterned structures. Fortunately both ASML and Nikon presented 193nm exposure tools with sub-nanometer CDU and intrinsic overlay capability. Both the ASML NXT:1970Ci and the Nikon NSR-630D promise throughput better than 250wph and improved stability in spite of illumination and reticle changes.

Cymer has upgraded the control software on their XLR660iX to improve stability, as well. Constant wavelength and bandwidth (E95% = 300fm +/- 5fm) is now maintained on every shot in a lot even though a gas refill. Metrology tools are being designed for sub-tenth-nanometer performance, according to Ady Levy of KLA-Tencor. So, if designers can stomach the design rules that come with SAQP and other multipatterning technologies, the way seems clear to 10nm and beyond, even without dramatic breakthroughs.



  • memister

    “Attempting to fabricate the cuts and vias with 193i multi-patterning would require 9 masks for one ~12nm level”

    This is because SAQP/cut/cut/cut/cut/cut/cut/cut/cut is the first and most easily imagined, brute-force approach. SAQP/cut/keep/cut works more efficiently: https://en.wikipedia.org/wiki/File:Triple_complementary_exposure.png

    Or else let the SAQP spacer define dielectric gaps instead of metal lines (SID instead of SIM). Then some of the double-patterned metal lines automatically cut the remaining ones without extra masks.