Why we need a synthesis tool set for SoC interconnects.
As chip designers, we take logic synthesis for granted. It’s hard to imagine the days when engineers had to design digital logic by hand. But then, it’s no less mind-boggling to believe that NASA engineers used slide rules to calculate and plan the Apollo 11 mission that first landed on the moon.
Were engineers just a whole lot smarter in the old days? Maybe. But it’s also true that chip designs have become much more complex, largely due to sophisticated tools such as synthesis, which actually enabled the rapid advances in semiconductor technology. However, today microprocessors are becoming yesterday’s news and SoCs are taking their place as the engine of digital progress.
Sadly, though, in some ways we are back to square one because most chip architects are still struggling to do their designs manually using spreadsheets and drawing tools like Visio. What we need is a new kind of synthesis that automates SoC design the way logic synthesis automated circuit design.
If we consider for a moment a “typical” SoC and some of the variables involved in configuring the system interconnect, the complexity problem becomes apparent. There are a large number of IP blocks to be connected, each with different interface protocols and widths, different clock-domains, different voltages and power-shutoff regions. Each has its own configurable properties such as the number of outstanding transactions, burst-sizes, burst-lengths, and so on.
Additionally, the traffic needs of the design must be taken into account, including a large number of varied bandwidth and latency requirements between communicating entities that vary across different operating scenarios. Tracking and manipulating such parameters rapidly descends into spreadsheet hell. Furthermore, it forces the architect to (artificially) partition the system into small subsystems upon which a “what-if” analysis can be performed on manually created implementations or models.
There has got to be a better way. We need a synthesis engine that could automatically generate an optimal on-chip interconnect for a given design. For example, we need to be able to define system requirements at a high level and automatically generate all of the many low-level parameters and design constraints and capture them in a well-defined language. With a synthesis engine, we could take advantage of network algorithms and machine learning techniques to automatically generate an on-chip interconnect in a fraction of the time.
A synthesis tool set for SoC interconnects could potentially give system architects many new capabilities for exploring new and more complex designs to better meet systems requirement. The new designs would be correct-by-construction, guarantee performance, and would be timing correct at tape out.
In future articles, we’ll look at how synthesis techniques can encompass more complex constraints such as physical awareness, quality-of-service, traffic isolation and deadlock avoidance.