All I Want For Christmas…
A design technology wish list.
As I write this, we’re heading into the 2016 holiday season. December 21 is also the shortest day of the year, so I better get right to the point.
2016 has been a year of many surprises. The spectacular consolidation in the semiconductor industry has permanently altered the landscape. It has created new, world-class capability and left a few gaps as well. 2.5D designs are finally moving into the mainstream. Yours truly has been predicting this for over a decade – I’m finally right. We’ve seen hard details about 7nm and 10nm process nodes, and real, believable discussion about 5nm and 3nm. Some are putting deep ultraviolet lithography to work (finally). Deep machine learning is now a real topic, with real chips and real applications. Autonomous behavior and natural language interfaces for all sorts of systems are moving into the mainstream – this was science fiction just a few short years ago.
There were surprises in other parts of the world – mostly the US and the UK from a political point of view. It would be interesting to dive into that and see how many comments I could generate, but I digress.
With all these ground-breaking technology innovations happening all around us, I feel compelled to draft a wish list of presents for a yet undiscovered technoSanta. Here goes…
- Lower wafer prices. Advanced designs are getting way too expensive. Custom chips used to be for everyone, but it’s not feeling like that anymore. I know it costs a fortune to build an advanced fab. Nonetheless, a break in wafer price would really help the market grow, I believe.
- Retro design. There’s still a lot that can be done in 65nm and above. Same technology, but much more advanced design styles. (This is not your father’s 65nm design.) I believe thoughtful use of mature technology nodes can open up significant new markets. eSilicon is privileged to be working on this topic with a very creative researcher. I believe this work will turn some heads. More on this later.
- Cloud-based EDA tools. It takes an obscene number of processor cores to build a finFET-class chip. The disk space required is also measured in many multiples of the space required to store all knowledge from the 1980s. This is forcing the brave few who undertake these designs to move to a scalable, cloud-based infrastructure. Except EDA licensing models are hard to adapt to this deployment. We’ve got to figure this out.
- 3D standards. It’s going to be hard to build true 3D stacks if there’s no standard specification to describe how that stack is put together. This is just one of many gaps in the emerging 3D chip market. We need thoughtful, tenacious people to fix this problem, and fast.
- OK, running out of time since the days are so short. Did I mention the need for lower wafer prices?