In the proper context, asynchronous logic in SoC design today can provide benefits. But what about impact on design tools and flows?
In the right situation, using asynchronous logic makes a lot of sense—especially for security and IoT. But moving into the asynchronous design involves making tradeoffs, figuring out how the technical requirements of an application will impact the design, and understanding the limits of EDA tools in this area.
“It’s going to be halfway between digital and analog support,” said Bernard Murphy, CTO at Atrenta. “The timing and traces become much more critical in asynchronous logic so you have to think of this. You could be doing not exactly SPICE level simulation, but you have to think about interconnect delays as well as gate delays, so forget about cycle-based simulation. That’s out the window. You’re going back to timing simulation with interconnect delays in some manner. Then I’m pretty sure you’re back to gate-level synthesis.”
It’s no better on the physical side, either. “When it comes to layout, I vaguely remember seeing a place and route tool for this, but again it was academic, not a commercial tool,” Murphy said. “It’s probably going to have to have a fair degree of custom control to move things around, and then you have to back annotate that back to your gate level simulation—not to mention replacing a whole generation of thinking about designing synchronous logic.”
It’s not just replacing the thought process. Steve Carlson, group marketing director in Cadence’s Office of Chief Strategy noted that the entire design automation ecosystem has been built around the mostly synchronous assumption.
“From the performance optimizations of the HDL simulators and synthesis optimization techniques down to the timing-driven place and route and sign-off multi-corner static timing analysis, all of the tools in the chain rely upon implicit and explicit assumptions about synchronous behavior,” Carlson said. “Trying to do fully asynchronous design with today’s tools has overt (such as having to specify many more timing constraints) and covert (such as the runtime penalty is event-driven simulation engines) issues.”
In fact, he noted that special techniques are required—read extra effort—to verify each asynchronous element of an SoC. “To make static timing sign-off work, the relationship between each storage trigger signal and generated data path must be checked. This is not to say the asynchronous design cannot be done with today’s design automation solutions. There are a few companies that have been designing and successfully manufacturing asynchronous chips for years. Also, you would be hard-pressed to find an SoC that is not a combination of synchronous and asynchronous behaviors.”
Furthermore, Paul Cunningham, vice president of R&D at Cadence, said the notion of a global clock is deeply ingrained in the entire digital tool flow. For example, the whole way timing analysis is done in synthesis, P&R, and sign-off assumes that a design is synchronous.
Marco Brambilla, director of engineering at Synapse Design, asserted that asynchronous design requires different design tools than are currently in use today. “There is no standard way of describing clockless logic. The common RTLs used (Verilog and VHDL) are not usable, or at least nobody figured out how as far as I know. If you do a Google search, you’ll see that no EDA company has even ventured into clockless designs. There are a few universities but no big names.”
He recalled one company, Fulcrum (acquired by Intel) that was working on clockless chips, but it used internally-developed chips.
“I also know one company that started as an EDA tool vendor, but is now making secure chips. The reason they moved from tools to circuits is not only because there is more money in selling products than tools, but also because it is much more difficult to create a flow. The company, which is closest to a tool-based solution, still had to invent a way to use a System Verilog TLM description to synthesize asynchronous logic. While this allows them to use standard simulators, their logic cannot be synthesized by a normal synthesis tool and requires a designer to learn a new design paradigm,” Brambilla continued.
Another significant issue occurs when doing the physical implementation. “The benefit of no longer having a clock becomes your curse,” he said. “You cannot assign constraints any longer. It becomes very difficult to predict the performances of your design and to optimize the PPA (Power/Performance/Area) of your chip. The Place & Route tool no longer knows how to decide which paths to optimize and how to time the circuit. The only guidance that can be given is to put a large number of max-delay constraints. I have no idea of how optimized this becomes in the ASIC.”
Brambilla pointed out the last main complication of clockless circuits is that there is no design for test solution he is aware of. “Again the absence of clocks makes scan chains unavailable and that also means that the ATPG tools no longer know how to generate the patterns, because they no longer understand the logic. It probably also becomes problematic when in production to screen for chips that perform at a certain minimum speed, as it is much more complicated to find a test that stimulates the slowest path (an equivalent to the transition faults, for example).”
At the end of the day, what may ultimately drive asynchronous logic use is power sensitivity, according to Mrugesh Walimbe, MTS Function Manager for SoC design at Open-Silicon. “I see a requirement of low power to drive this more than speed or noise/EMI considerations. I do not see a requirement in the near future. However, with low-power design becoming the primary spec, it will eventually be looked at as a serious option for implementing some parts of a function.”