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Quantum Well Design Basics
By Cadence - 10 Apr, 2024 - Comments: 0

Key Takeaways The choice of materials for the quantum well and barrier layers is paramount. Materials must have compatible lattice structures to minimize defects, with common combinations including GaAs/AlGaAs, InGaAs/InP, and GaN/AlGaN. The width of the quantum well significantly influences the energy levels and density of states, where narrower wells result in greater separation betwe... » read more

What’s At Stake In System Design?
By Cadence - 03 Apr, 2024 - Comments: 0

When engineers refer to system analysis, they are referring to tool functions for improving an overall electronics design. What you will gain from this eBook: Power and Signal Integrity Insights into harmonic balancing and crosstalk analysis Learning about loop gain and transmission rates Examining the necessity of power-aware systems Electromagnetic Analysis Knowledge ... » read more

Cadence Cerebrus In SaaS And Imagination Technologies Case Study
By Cadence - 27 Mar, 2024 - Comments: 0

Artificial Intelligence (AI) has made noteworthy progress and is now ready and available for electronic design automation. The Cadence Cerebrus Intelligent Chip Explorer utilizes AI—specifically, reinforcement machine learning (ML) technology—combined with the industry-leading Cadence digital full flow to deliver better power, performance, and area (PPA) more quickly. However, this highl... » read more

Overcoming Signal Integrity Challenges Of 112G Connections
By Cadence - 13 Mar, 2024 - Comments: 0

One of the big challenges with 112G SerDes (and, to a lesser extent, all SerDes) is handling signal integrity issues. In the worst case of a long-reach application, the signal starts at the transmitter on one chip, goes from the chip to the package, across a trace on a printed-circuit board (PCB), through a connector, then a cable or backplane, another connector, another PCB trace, another pack... » read more

3D Connection Artifacts In PDN Measurements
By Cadence - 28 Feb, 2024 - Comments: 0

Authors: Ethan Koether, Amazon; Kristoffer Skytte, John Phillips, Shirin Farrahi, Cadence; Joseph Hartman, Oracle; Sammy Hindi, Ampere Computing Inc.; Mario Rotigni, STMicroelectronics; Gustavo Blando, Istvan Novak, Samtec From a simulation stand-point, we have covered several important topics that users must consider in detail to get accurate low frequency simulation results. We investigate... » read more

Sigrity X — Redefining Signal And Power Integrity
By Cadence - 14 Feb, 2024 - Comments: 0

This white paper highlights the features in Cadence Sigrity X signal and power integrity (SI/PI) solutions for system-level SI and PI analysis that enable designers to cut the number of design respins and meet short time-to-market windows with confidence. Click here to read more. » read more

FMEDA-Driven SoC Design Of Safety-Critical Semiconductors
By Cadence - 31 Jan, 2024 - Comments: 0

As state-of-the-art electronics propel the automotive, industrial, and aerospace industry into a future of more connectivity and autonomy, the development of safety-compliant semiconductors is critical. The Cadence FMEDA-driven Safety Solution consists of products enhanced for advanced safety analysis, safety verification, and safety-aware implementation for digital driving analog and dig... » read more

Machine Learning Based MBIST Area Estimation
By Cadence - 03 Jan, 2024 - Comments: 0

Majority of the silicon with-in a design is occupied by memories. Memories are more prone to failures than logic due to their density. Several techniques have been established to target and detect defects within these memory instances and their interfacing logic. The most widely used approach is memory built-in self-test (MBIST) that inserts on-chip hardware unit(s) which provides systematic me... » read more

System-Driven PPA For Multi-Chiplet Designs
By Cadence - 20 Dec, 2023 - Comments: 0

As we approach the device scaling limitations at advanced nodes, the demand on compute performance and data transfer for hyperscale data center and AI designs is at an all-time high. Advanced systems-on-chip (SoCs) are reaching reticle size limits, and there has been a need to find innovative solutions to continue Moore’s law scaling and achieve performance improvements with reduced power. St... » read more

Demystifying Mixed-Signal Simulation For Digital Verification Engineers
By Cadence - 13 Dec, 2023 - Comments: 0

The convergence of analog and digital technologies on a single chip, commonly referred to as mixed-signal, has reshaped the integrated circuit (IC) landscape. In recent years, mixed-signal designs have emerged as the dominant technology, therefore requiring traditional analog and digital methodologies to be enhanced. A mixed-signal design offers many advantages, including boosted performance, r... » read more

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