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The Week In Review: Design

Tools Synopsys debuted new versions of its circuit simulation and custom design products. FineSim SPICE provides 2X faster simulation and Monte Carlo analysis speed, CustomSim FastSPICE offers 2X speed-up for post-layout SRAM simulation and maintains multi-core scalability by providing additional 2X speed-up on four cores, and HSPICE delivers 1.5X speed-up for large post-layout designs, accord... » read more

Blog Review: Mar. 14

Cadence's Meera Collier considers the issues of bias implementation in algorithms and AI systems, and whether immense training sets can really solve the problem. Mentor's Cristian Filip digs into the evolution of signal integrity analysis methods and why different data rates require different solutions. Synopsys' Naveen G explains key features introduced in the latest generation of interc... » read more

Power/Performance Bits: Mar. 13

Wireless charging Engineers at the University of Washington developed a method to safely charge a smartphone wirelessly using a laser, potentially as quickly as a standard USB cable. Safety features of the system include a reflector-based mechanism to shut off the laser and heatsinks. The charging beam is generated by a laser emitter that the team configured to produce a focused beam in the... » read more

The Week In Review: Design

M&A Microchip inked an agreement to acquire Microsemi, provider of chips for defense and aerospace, for $68.78 per share in cash. The acquisition price represents a total equity value of about $8.35 billion and a total enterprise value of about $10.15 billion, according to Microchip. The deal is expected to close in the second quarter of 2018. Silvaco acquired NanGate. Founded in 2004, ... » read more

Blog Review: Mar. 7

Synopsys' Amit Paunikar and Shaily Khare take a look at new features in LPDDR5, from improved data bandwidth and Deep Sleep Mode to WCK clock. Cadence's Paul McLellan dives into forward error correction, a technique for automatically correcting errors in transmitted network data, with a look at why it's important and how it works. In his latest embedded software video, Mentor's Colin Wall... » read more

Power/Performance Bits: Mar. 6

Neural network chip Neural networks are both slow and consume a lot of power. This made researchers at MIT examine the important aspects of the nodes within a neural network¬†and to see how each part of the computation could be improved. The outcome was a dedicated chip that increases the speed of neural-network computations by three to seven times over its predecessors, while reducing power c... » read more

The Week In Review: Design

Startup OnScale launched with advanced CAE multi-physics solvers that are seamlessly integrated with a scalable, high performance cloud computing platform built on Amazon's AWS. The company's model is built around a Solver-as-a-Service pay-as-you-go subscription model and targets 5G, IoT/Industrial IoT, biomedical, and autonomous car markets. The company has $3 million in strategic seed fund... » read more

Blog Review: Feb. 28

Mentor's Matthew Ballance explains just what the portable stimulus standard makes portable. Cadence's Dave Pursley considers why high-level synthesis is a good fit for cutting-edge machine learning designs. Synopsys' Melissa Kirschner notes that the growing number of IoT devices means new opportunities for one-time programmable NVM. Applied's Mike Rosa considers the pros and cons of 5G... » read more

Power/Performance Bits: Feb. 27

Encryption chip A team at MIT developed a new chip to lower the power consumption of public-key cryptography for IoT devices. Software execution of encryption protocols require more energy and memory space than embedded IoT sensors can typically spare, given the need to maximize battery life. The new chip is hardwired to perform public-key encryption and consumes only 1/400 as much power as... » read more

The Week In Review: Design

Tools & IP Pro Design launched three new proFPGA Zynq UltraScale+ FPGA modules for SoC and IP prototyping. The modules combine FPGA logic with quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5 processors and on-board interfaces. The modules offer a total of up to 5 extension sites with 531 standard I/Os and 16 multi-gigabit transceivers (MGTs). The board allows a maximum point-to-point ... » read more

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