Author's Latest Posts


The Veloce Strato Platform: Unique Core Components Create High-Value Advantages


The Veloce Strato Emulation platform has sufficient execution speed, full visibility capabilities and ease-of-use in model creation and model updates to span the entire range of needs throughout the life of the design development process. To read more, click here. » read more

Putting “Design” Back Into Design For Test In PCB Products


Design for manufacturing (DFM) has become a proactive part of the design process, but the same cannot be said for DFT. Whereas “left-shifting” DFM has reduced manufacturing problems, increased yield, reduced scrap levels, and simplified engineering rework, testability-related improvements have stayed flat during that same time. Unfortunately, as assembly costs have come down, and test-relat... » read more

18th Century Technology For Modern Medical IoT


Back in 1790, Luigi Galvani was dissecting a frog and noticed that he could cause its leg to move when touching a nerve with two probes. He called this phenomenon “animal electricity.” This concept was soon refined over time to become the voltaic cell, the foundation concept of the potato clock, fondly known by all engineers. Who knew that this cell would be leveraged to create an ingestibl... » read more

Choosing A Format For The Portable Stimulus Specification


The Accellera Systems Initiative is currently defining a Portable Stimulus Specification (PSS) standard for verification models that can be used to generate appropriate tests for all levels and platforms automatically. The current draft of the standard includes two alternative input formats for these models. This paper examines the merits and challenges of both formats. To read more, click h... » read more

Alchip Minimizes Dynamic Power For High-Performance Computing ASICs


Alchip, a fabless ASIC provider, focuses on high-performance computing ASICs. They decided to undertake a new project where they would employ the PowerPro RTL Low-Power Platform to reduce dynamic power consumption within their unique fishbone clock tree methodology. Could they achieve better power results using PowerPro and could they integrate the tool within their team and the existing design... » read more

Package Designers Need Assembly-Level LVS For HDAP Verification


While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique package connectivity issues, such as missing or misplaced interposer/package bumps/pads, pin naming and text labeling issues, and the like, require new and enhanced LVS-like verification techniques that can move across the entire package to ensure proper connectivity and perfo... » read more

Engineering Challenges for Viable Autonomous Vehicles


The rise of autonomous and electric vehicles brings with it a host of engineering implications, including an increase in the number and variety of sensors in the vehicle, increasing software and hardware complexity, massive validation and verification cycles, heightened safety and security requirements, and new demands for digital data continuity. This paper is an overview of how six interdisci... » read more

8 Checks That Every PCB Designer Needs To Achieve Electrical Sign-Off


Automate electrical design rule checking (DRC) for fast, cost-effective PCB design verification. These eight rules apply regardless of your PCB layout tool or level of expertise. To read more, click here. » read more

Ultra-Low Power Memory IPs Using Mentor coolSRAM-6T Technology


The use of embedded static random access memory (eSRAM) in complex ICs has significantly increased in the past three decades. This trend will continue with the growth of ICs designed for rapidly expanding markets such as automotive, virtual reality (VR) / augmented reality (AR), implantable medical devices, gaming, sensor hub, medical devices, wearable computing, data center, and artificial int... » read more

Functional Safety In AI-Controlled Vehicles


Whereas ISO 26262 specifies requirements for eliminating safety hazards in the presence of an E/E system fault, this paper explains why new standards for the AI era must address so-called safety of the intended functionality (SOTIF), which means helping to validate that advanced automotive functionalities are engineered into the vehicle to avoid safety hazards even in the absence of a fault. ... » read more

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