Author's Latest Posts


The Democratization Of CFD


“Democratization” is a buzzword that has been circulating around the Computational Fluid Dynamics (CFD) community for some time. In this White Paper, Keith Hanna and Ivo Weinhold of Mentor Graphicsdefine the issue, establish the facts, look at the pros and cons of various technology solutions being offered in the market today, and then suggest some pointers for the future as the CFD industr... » read more

Virtual PCIe Delivers A “Shift Left” In Software-Defined Networking Emulation


This paper reviews both SW and UVM Vector Based Verification (VBV) methodologies and Advanced Vector Based Verification (AVBV) that uses Software Defined Networking (SDN) HW to service PCIe transactions to the DUT. When deploying VBV methodologies, using the Veloce Transactor Library (VTL) family of components is most appropriate for UVM, C++ and SDK testbench methodologies. We explore how V... » read more

Building Functional Safety And Security Into Medical IoT Devices: IEC 62304 Conformance


As the IoT marches on – security and safety issues continue to be a top priority for embedded systems developers. Building security into your medical IoT device not only helps to reduce the chance of a data breach or cyber attack, but also introduces new ways to optimize software, reduces time to market, and increases the potential for product innovation in a very competitive global market. ... » read more

Rapid SoC Proof-Of-Concept For Zero Cost


A new breed of designers has arrived that is leveraging inexpensive sensors to build the intelligent systems at the edge of the Internet of Things (IoT). They work in small teams, collaborate online, and they expect affordable design tools that are easy to use in order to quickly produce results. Their goal is to deliver a functioning device to their stakeholders while spending as little money ... » read more

Power Management Validation


Power consumption is becoming a critical aspect of hardware design. No longer is verifying an SoC solely answering the question “does it work?” Now designers must also answer the question “does it meet my power budget?” When trying to find power issues it is critical to run the complete system in a realistic manner—at the system-level when the design/verification team is looking at th... » read more

The Final Days…Getting To Sign-Off Faster With Calibre


With deadlines looming, the design flow between router output and final tape release can be stressful and frustrating. By combining a focused set of commands into macros, the Calibre YieldEnhancer tool enables designers to create customized, automated flows for engineering change order (ECO) filling, passive device insertion, custom fill to increase densities, jog removal, and via enhancements.... » read more

7 Design Aspects of IoT PCB Designs


To consumers, IoT devices look sleek and simple, but they are comprised of a distinct set of components, physical interfaces, PCBs, and circuitry that presents unique design and layout challenges. This paper looks at seven things to consider when designing PCBs for successful IoT devices. To read more, click here. » read more

IP Qualification with Oasys-RTL


With increasing design sizes and complexities, the use of IP (intellectual property) as basic building blocks for better SoC design is also increasing. This paper presents the challenges faced during IP integration at the SoC level and what can be done to mitigate those risks during IP development. Mentor’s Oasys-RTL RTL floorplanning and physical synthesis tool offers a unique IP qualificati... » read more

How Formal Reduces Fault Analysis For ISO 26262


The ISO 26262 standard defines straightforward metrics for evaluating the “safeness” of a design by defining safety goals, safety mechanisms, and fault metrics. However, determining those metrics is difficult. Unlike simulation where it is never known if the design has been simulated enough or given enough input, formal verification conclusively determines if faults are safe or not, making ... » read more

Implementing Fan-Out Wafer-Level Packaging with Mentor Graphics


Fan-out wafer-level packaging (FOWLP) is a new high-density packaging technology that is rapidly gaining popularity. What is it? Who needs it? How do you take advantage of it? What limitations does it have? Learn all about FOWLP and our comprehensive tool integration and support for the design and verification of FOWLP products. To read more, click here. » read more

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