Why analytics are critical to the future of semiconductor design.
For the last two decades I have spent a lot of my time managing operations and sales for several EDA startups, most of which were acquired. The focus of many of these companies was to provide solutions to optimize complex designs. We worked to enhance many of the top 25 semiconductor companies’ physical implementation flows using cutting edge technologies and methodologies to improve power, performance or area.
The solutions ranged from manipulating wire load models to swapping cells on the critical path. In many cases, the final benefits were limited as the design taped out because of various pre-selected IPs such as memories that reduced the gains in logic optimization.
I had many discussions with my customers around these issues — if only we could provide technology to facilitate better IP choices earlier in the flow so that improvements in physical design would be more impactful. Many customers taped out a suboptimal design in order to meet time-to-market pressures and get some revenue before being hurt by the lost opportunity associated with being late.
Technology choices were also challenging. The most notable stories are those where a company decided on a process node a little too quickly and ended up spending tens of millions of dollars only to realize that their design didn’t fit that node. Eventually, the entire process node was skipped for a newer, more expensive and potentially better yielding process node. The R&D costs were high, but the cost of lost revenues even higher. Sometimes, a whole division was reduced or even eliminated to keep profit margins high enough for Wall Street.
Not long ago, I joined eSilicon and the semiconductor side of the business. I have been quite encouraged by what I see. The design virtualization technology recently announced by the company closely resembles what my customers wished they had during the challenging times I’ve mentioned. Inappropriate IP and technology choices can neutralize the most advanced design techniques and EDA tools. I’ve seen it happen. The ability to understand, early in the design process, the impact of IP and technology choices on power, performance and cost for the design can be the margin of victory.
This is my third week on the job. I started on the first day of DAC, which seemed appropriate. During my first weeks here, I’ve seen encouraging technology. Technology that can make a difference in the return on investment for a complex design. At DAC, I heard about several other novel approaches to improve chip design results. All of these techniques are rooted in big data analytics, a new buzzword for our industry that I believe holds great promise.
These technologies have been deployed in other industries for a while now, but they are new to the semiconductor industry. If you’ve ever regretted an IP or technology choice when you’re a week away from tapeout, take a close look at big data analytics and the crop of new tools from eSilicon that promise the ability to predict the future. You might find some big opportunities as a result. You can check out what eSilicon is up to with big data and online technologies here.