Blog Review: April 5

Neural network architecture; verification and safety; SerDes signal integrity; panel-level fan-out packaging.

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In a video, Cadence’s Megha Daga digs into the different architectural layers present in convolutional neural networks and how they contribute to object detection and classification in a real world scenario.

Mentor’s Mike Santarini argues that as things become increasingly connected, the stakes of bad design and bad verification are higher than they’ve ever been.

Synopsys’ Robert Vamosi warns of the dangers of connected dishwashers, where vulnerabilities could potentially compromise hospital networks.

Ansys’ Sandeep Sovani looks at how simulation can provide the billions of miles of testing needed to prepare autonomous cars for the road.

Rambus’ Aharon Etengoff points out some of the challenges in maintaining SerDes signal integrity as data rates approach 56Gbps.

National Instruments’ James Kimery points to a recent study testing one potential component of 5G, Massive MIMO, in real-world conditions at the University of Bristol.

ARM’s John Shockley has some fun building a Raspberry Pi-based Aircraft Tracker and taking it on a test flight.

Lam Research’s Choon Lee, Tom Bondur, and Manish Ranjan examine the cost and performance challenges in the use of panel substrates for fan-out wafer-level packaging.

Aldec’s Krzysztof Szczur argues for using a software-driven verification methodology in an FPGA prototyping environment.

Cadence’s Paul McLellan chats with Lucio Lanza about the possibility of crowd sourcing analog design, allowing designers to work dispersed around the globe.

In a video, Mentor’s Colin Walls gives a brief introduction to memory management units in embedded systems and how they can lead to more secure software.

Synopsys’ Tom De Schutter shares some highlights from the recent SNUG Silicon Valley.