Blog Review: Aug. 31

Mentor’s Harry Foster presents the 2016 Wilson Research Group Functional Verification Study, beginning with trends in FPGA design and an investigation into the verification effort it takes.

Synopsys’ Viral Sharma warns that while AMBA AXI exclusive access may look simple at first glance, the possibility of different scenarios and combinations poses a challenge.

Cadence’s Paul McLellan looks at a big problem finFETs face: accelerated aging effects caused by self-heating.

Rambus’ Aharon Etengoff notes that while quantum computing may offer myriad advancements, architecture and memory requirements play a role in its potential.

From performance optimization to system reliability, NXP’s Nik Jedrzejewski highlights three ways embedded heterogeneous systems can be beneficial to designs.

Verification blogger Gaurav Jalan chats with Mentor’s Wally Rhines about the new requirements facing verification and moving beyond high-level synthesis.

ARM’s Peter Harris digs into the details of the Mali Bifrost GPU architecture and what performance expectations application developers should have.

Mentor’s Karen Chow examines the perils of electromigration and gives some advice on how to determine if a design is safe.

Synopsys’ Hezi Saar checks out what’s behind Microsoft’s 28nm custom vision processor SoC targeting augmented reality headsets.

And if you missed last week’s System-Level Design newsletter, check out these featured blogs:

Editor In Chief Ed Sperling finds semiconductor companies crossing lines in ways no one ever would have expected.

OneSpin’s Dave Kelf points to problems of the past as a way to build versatile formal apps.

Cadence’s Frank Schirmeister contends that designers need to look beyond just power, performance and cost.

Arteris’ Kurt Shuler argues that ‘fixing it in software’ adds bloat and that transistor scaling slows things down.

ARM’s Nigel Stephens explains what vector processing has to do with big data and why it’s so important.

NetSpeed Systems’ Rajesh Ramanujam drills into the value of last level cache.

Synopsys’ Malte Doerper observes that keeping the right focus maximizes virtual prototyping ROI.

eSilicon’s Mike Gianfagna contends that when it comes to automation, things are just getting started.

Mentor Graphics’ Kathy Tufto finds debug approaches are changing to handle the amount of data produced by multicore systems.

Aldec intern Zach Nelson provides a student’s view on utilizing FPGA boards in education.