Safety critical designs and silicon success; modeling software risk; MTV Workshop highlights; MEMS growth; comparing compilers with ARM models.
Mentor’s Harry Foster wraps up his functional verification study series with a look the impact of verification maturity and safety critical designs on first silicon success.
Synopsys’ David Benas argues for using the insurance industry as a model in assessing the risk of potential software flaws.
Cadence’s Tom Anderson shares highlights from the recent International Workshop on Microprocessor and SOC Test and Verification.
Applied’s Mike Rosa looks at the rapid growth in MEMS during 2016 and the factors driving the need for new MEMS device technologies.
ARM’s Jason Andrews provides a tutorial on using ARM Cycle Models to compare compiler performance.
Semico’s Seth Itow says that for lithium ion batteries to be made safer, ICs designed specifically for creating battery management systems need to come down in cost.
Ansys’ Susan Coleman has a list of five startup-focused events happening in the first half of 2017.
Rambus’ Aharon Etengoff checks out how biometric authentication is growing in banking, and paying for lunch at work.
Cadence’s Paul McLellan looks back at the early days of design automation with DAC founder Pat Pistilli.
And don’t forget the featured blogs from the latest edition of the System-Level Design newsletter:
Editor In Chief Ed Sperling contends that mathematics has confused everyone since the dawn of civilization.
Technology Editor Brian Bailey finds no end to things people think are worth patenting.
Mentor Graphics’ Geir Eide shows why cell-aware diagnosis is useful for finding problems at leading-edge nodes, and for everyone else.
Synopsys’ Malte Doerper compares virtual prototyping to cooking because it can be learned by focusing on a few key elements.
Cadence’s Frank Schirrmeister predicts that verification will become a whole lot smarter next year.
Arteris’ Kurt Shuler explains how to keep your skills up to date to avoid missing automotive opportunities.
Aldec guest blogger Espen Tallaksen examines how to verify programmable chips faster, with better quality, and at no extra cost.
eSilicon’s Mike Gianfagna uncorks a design technology wish list.
OneSpin’s Dave Kelf provides a classic logic puzzle for the holidays.