Neural network basics; pseudo-hierarchical DFT; zero day vulnerabilities; medical security; DVCon China.
In a video, Cadence’s Megha Daga introduces how convolutional neural networks identify objects and the wide range of applications for the technology.
Mentor’s Ron Press proposes a way to take advantage of hierarchical DFT features, even if a design wasn’t designed for it.
Synopsys’ Robert Vamosi shares highlights of the RAND Corporation’s extensive report examining zero day vulnerabilities.
Rambus’ Aharon Etengoff argues for the necessity of protecting medical implants against malware and side-channel attacks.
Independent blogger Gaurav Jalan introduces the first year of DVCon China, to be held April 19, 2017, with a brief overview of the country’s growing impact on the semiconductor industry.
Sonics’ Randy Smith looks at how IP can support Agile hardware design methodologies.
ARM’s Charles Dittmer shows what goes into building a Bluetooth-enabled smart parking meter.
Cadence’s Paul McLellan considers differentiation in automotive and whether, like smartphones, top companies are willing to design their own silicon.
Mentor’s Mike Santarini suggests that while what a system is depends on perspective, more closely coordinated efforts between disciplines will lead to even greater innovation.
Synopsys’ Anand Thiruvengadam chats with Samsung’s Parvinder Rana about last month’s AMS SIG India event.
Plus, check out the blogs highlighted in last week’s System-Level Design newsletter:
Editor in Chief Ed Sperling observes that it’s getting harder even for big chip companies to get designs out the door on time.
Technology Editor Brian Bailey contends that the standard for verification modeling has a misleading name, and it should be changed.
Aldec’s Igor Gorokhov digs into FPGA-based use cases for reference designs.
OneSpin Solution’s Dave Kelf finds that applying formal techniques to a classic logic puzzle results in plenty of creative solutions.
Mentor Graphics’ Jeff Miller points to the need for a low-cost proof-of-concept in IoT design.
ARM’s Nandan Nayampally examines how to boost performance with the same power envelope.
ESD Alliance’s Bob Smith looks at trends, opportunities, danger signs, and the future of semiconductor design.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply