Blog Review: Nov. 4

Agile chips; embedded language standardization; space adventures (and spiders); ARM TechCon; Avago CEO observes the industry; Halloween cheer; CDCs & DO-254; counterfeit auto parts.


Can agile methodologies typically used in software development bring more efficiency to chip design? For UC Berkeley Professor Borivoje Nikolic, the answer is, why not? Christine Young reports on the keynote at Cadence’s Mixed-Signal Technology Summit.

For his latest embedded video, Mentor’s Colin Walls focuses the camera on language standardization and use of language extensions.

Ansys’ Bill Vandermark keeps an eye on the sky in this week’s top five engineering tech articles. NASA’s Dawn probe is reaching final orbit distance just 230 miles from dwarf planet Ceres, and the space agency has chosen an imager for the 2020 Mars rover. Plus, construction is almost finished on the latest Virgin Galactic spacecraft.

On Mars, spiders might be man’s best friend: their silk shows promise as optical fibers ideally suited to detecting possible signs of life on the red planet. Rambus’ Aharon Etengoff takes a look at the study.

If you’re headed to ARM TechCon next week, Brian Fuller has the rundown of a few things not to miss. And if you aren’t (yet), discounted registration is still available for a few more days.

Cadence’s Paul McLellan attended the Chinese American Semiconductor Professional Association annual conference and dinner, where Avago CEO Hock Tan presented his top ten observations of the industry.

Mentor’s Robin Bornoff spins a spooky Halloween tale, while Ansys’ Anatole Wilson has the latest on simulating the paranormal.

While the does RTCA/DO-254 guidance says nothing about clock domain crossings, Aldec’s Louie De Luna digs into the havoc CDCs can cause DO-254 FPGA projects.

Counterfeit automotive parts are a serious problem that’s only grown worse in recent years, and is now considered a global phenomenon, says NXP’s Mahdi Mekic.

Plus, check out last week’s featured blogs in our System-Level Design newsletter:

Editor In Chief Ed Sperling looks at what happens after the smartphone market flattens out.

Technology Editor Brian Bailey takes aim at badly written and inefficient software, arguing it delays the move to better hardware architectures.

eSilicon’s Mike Gianfagna finds ideas for the next big things are showing up in different places than in the past.

Synopsys’ Tom De Schutter questions why you would develop software in the dark after conducting an unusual experiment.

Cadence’s Frank Schirrmeister observes that demand for more efficient emulation utilization is growing.

Mentor’s Robin Bornoff explains how to limit power loss and what to watch out for.

Arteris’ Kurt Shuler concludes that if you can’t optimize your interconnect, you’ve neglected this area too long.

Aldec’s Doug Amos digs into how to improve pre-silicon verification and validation.