The opportunity exists for further improvement in RTL Power Estimation accuracy with physical-aware techniques.
The power targets for today’s complex SoC designs force design teams to address power optimization earlier and more effectively than ever before. In recent years, design teams have migrated to RTL power estimation solutions to identify areas of potential power savings to be used in early design tradeoffs. RTL power estimation accuracy at 15% to 20% to gate-level power numbers is deemed acceptable.
This level of accuracy is achieved through technology library mapping and statistical calibration models. Generally, the calibration model contains elements for clock topologies, interconnect capacitance, and cell distribution. Creation or refinement of the model will be based on mining previous design data. The calibration models are generally a good fit for similar design applications, but accuracy diverges as design characteristics shift from this calibration point. Therefore, this approach requires multiple calibration models to be maintained across design families.
How can we improve on the accuracy provided by the calibration model? Switching power is based on CV²F, so better accuracy for design capacitance inherently will improve accuracy of power estimation. The introduction of physical-aware techniques can provide this benefit.
The natural concern for any physical-aware solution is runtime. Certainly there will be an impact, but overhead should be manageable based on the latest advances in physical implementation technologies, especially when compared to time required for gate-level analysis.
There are two main advantages in utilizing physical-aware techniques:
What if, by using physical-aware techniques, the accuracy of RTL power estimation can be improved to within 5% to 10% of gate-level power? Design teams will have higher confidence in the effectiveness of design tradeoffs on total power savings.