Industry Heavyweights Eye High-Speed DDR4 Server DIMM Chipsets


DDR3 server DIMM chipsets (800 Mbps) first hit the market in 2006 and began to ramp the following year. By the time DDR4 server DIMM chipsets (2133) began shipping in 2014, DDR3 server DIMM chipsets were spanning the following five speeds: 800, 1066, 1333, 1600 and 1866. In the last years, DDR4 buffer chipset shipments have crossed over in term of volume, with DDR4 chipset speeds expected to... » read more

NVDIMM Market Buoyed By Evolving Data Center Demands


The NVDIMM market A recent report published by Transparency Market Research (TMR) confirms that the global Non-Volatile Dual In-line Memory Module (NVDIMM) market is being propelled by an increased demand for advanced data center infrastructure. Indeed, NVDIMMs offer fault-tolerant data integrity, while simultaneously optimizing the performance of storage and cache, as well as indexing, messag... » read more

Enabling Higher System Performance With NVDIMM-N


The shift from the traditional enterprise data center to the cloud is driving an insatiable demand for increased bandwidth and lower latencies. This is fundamentally reshaping traditional memory, storage, network and computing architectures. Although the semiconductor industry has been innovating to meet the needs of these new architectures, it continues to grapple with a waning Moore’s Law t... » read more

Memory Buffer Chips: Satisfying Amdahl’s Law To Sustain Moore’s Law


Moore’s Law, the observation that the available transistors in an integrated circuit doubles every two years, has driven the semiconductor and IT industries to unparalleled growth over the last 50+ years. These transistors have been used in CPUs to increase the number of parallel execution units and instruction fetches, expand the levels of on-chip cache (and overall capacity), support spe... » read more

From SerDes Chiplets To Die-To-Die Interfaces


The demand for ever faster high-speed interfaces has never been quite so pronounced. In our increasingly connected world, petabytes of data are continuously generated by a wide range of devices, systems and IoT endpoints such as vehicles, wearables, smartphones and even appliances. The resulting digital tsunami has prompted industry heavyweights like Google, Microsoft, Facebook and Amazon to co... » read more

The SerDes – Terabit Ethernet Connection


400 Gigabit Ethernet (400GbE) and 200 Gigabit Ethernet (200GbE) are currently slated for official release by the IEEE P802.3cd Task Force in December 2017. Although there is not yet an official IEEE roadmap detailing what lies beyond 400GbE, doubling to 800GbE will likely become a reality when single-lane 112Gbps links hits the market. This technology will allow for larger lane bundles, providi... » read more

Understanding SerDes Signal Integrity Challenges


Signal integrity (SI) can perhaps best be defined as a set of measures of the quality of electrical signals, which are subject to the effects of noise, distortion and loss. Additional signal integrity issues include jitter, ringing, crosstalk, ground bounce and power supply noise. There are multiple factors that can negatively influence signal integrity, thereby causing errors and system fai... » read more

HBM2: It’s All About The PHY


HBM DRAM is currently used in graphics, high-performance computing (HPC), server, networking and client applications. HBM, says JEDEC HBM Task Group Chairman Barry Wagner, provides a “compelling solution” to reduce the IO power and memory footprint for the most demanding applications. Recent examples of second-generation HBM deployment include NVIDIA’s Quadro GP100 GPU which is paired wit... » read more

The Challenges Of Designing An HBM2 PHY


Originally targeted at the graphics industry, HBM continues to gain momentum in the server and networking markets as system designers work to move higher bandwidth closer to the CPU. Expanding DRAM capacity – which boosts overall system performance – allows data centers to maximize local DRAM storage for wide throughput. HBM DRAM architecture effectively increases system memory bandwidth... » read more

The Challenges Of Designing 28G And 56G SerDes IP


The industry move to 56 Gbps PAM4 is undoubtedly one of the greatest challenges currently facing SerDes IP designers and their customers. To begin with, shifting to 56 Gbps PAM4 immediately causes a loss of 9 dB. While the baud rate is 28 Gbaud, there are now three eyes stacked on top of each other. Nevertheless, there is still demand for 35+ dB reach. This is a significant challenge which requ... » read more

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