Modeling High-Performance Analog And RF Circuits In Nanometer-Scale CMOS

By Mick Tegethoff and David Lee Today’s consumer, communication, and computer electronic devices have clocks, communication interfaces, and high-speed signal-conditioning circuits that operate at radio frequencies (RF). Providing price-competitive products often requires monolithic integration of these circuits in low-power nanometer-scale bulk CMOS silicon. This is a worst-case scenario for... » read more

Calibrating Electronics Thermal Simulation Models

‘Rubbish In, Rubbish Out’ is a common and well-accepted fact in the world of thermal simulation—actually any type of simulation, for that matter. Regardless of the technical capabilities of your thermal simulation tool, the accuracy of prediction will always be tightly coupled to the accuracy of the input data. In terms of electronics thermal simulation, the prediction of the internal ... » read more

IGBT Power Cycling And Lifetime Testing

I have never been very good at introducing topics. During my presentations, I either jump directly into the subject matter, or start with a joke. My mom always said I could be a stand-up comedian. I prefer to sit. Oddly, that led me to becoming an engineer. And while this introduction does not lead me any closer to my actual topic, I presume some people rolled their eyes back and crossed their ... » read more

User Case Study

Whenever more than one clock is employed in an SoC (which is all SoCs), the risk of errors from clock domain crossings (CDC) – signals (or groups of signals) that are generated in one clock domain and consumed in another – is incredibly high. Unfortunately, CDC bugs are nearly impossible to catch with conventional simulations. Thus, all too often they escape into silicon. Debugging them in ... » read more

Extending Power Analysis To The Emulation of Complex SoCs

Using hardware emulation to estimate SoC power consumption delivers significant value. Emulators are capable of long runs on large designs, making it practical to emulate an RTOS boot sequence or graphics processing of multiple frames. Estimating power consumption of these advanced functions executing across the complete SoC provides valuable insight into the chip’s power draw and its impact ... » read more

The Revolution Will Not Be Televised: It Will Be On Your Phone

The advent of smart devices has ushered in a revolution all over the world. The most widely used smart device is the mobile phone, which has radically changed the way we communicate. There are many other types of devices running 24/7 in our homes, hospitals, businesses, etc. No matter what kind of functionality smart devices have, they have one thing in common: they all consume energy. They ... » read more

As Nodes Advance, So Must Power Analysis

By Chetandeep Singh and Ravi Tangirala Smaller geometry nodes offer cost and performance advantages that encourage their adoption. Yet they present a new set of challenges for IC manufacturers: Though transistors are smaller, they leak more current. This is an important issue as the demand for high-performance, battery-operated, system-on-chips (SoC) in communication and computing shifts th... » read more

Power Management Considerations For Efficient Embedded Systems Development

Usable product life is a critical factor in the success of any portable device, and managing power efficiency is a key requirement for embedded systems today. Historically, power management was seen as a “hardware problem” that plagued development teams, but with today’s sophisticated devices and more specialized hardware, this impacts the software developer, as well. One reason for this ... » read more

A High-Level ‘How To’ Guide For Effective Chip-Package Thermal Co-Design

By John Parry and Byron Blackmore Concurrent design of a chip and its packaging environment is becoming more important than ever for several reasons. Designing a large, high power die, e.g. a System-on-Chip (SoC), without considering how to get the heat out is likely to lead to problems later on, resulting in a sub-optimal packaging solution from cost, size, weight and performance perspective... » read more

Power Grid Simulation

Introduction The underlying solver algorithms used in power grid (PG) simulation today are derivations of circuit simulation algorithms first developed many decades ago. In fact, the 40th anniversary of SPICE (a widely used circuit simulator), was celebrated in 2011. As such, it is understandable that many engineers have a jaundiced view towards claims of improved PG simulation performance. Ne... » read more

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