Can A Supply Chain Be Too Efficient?


The semiconductor industry is a model of efficiency—literally. When other industries look at adding smart manufacturing into their operations, they often look to chip manufacturing as a shining example. After decades of business gyrations, semiconductor companies have figured out how to instill efficiency into every aspect of making chips. This is evident in device scaling. At 90nm, the co... » read more

5 Takeaways From Semicon


At the recent Semicon West trade show in San Francisco, there were a multitude of presentations on a number of subjects. The event, sponsored by SEMI, had presentations on the outlook for ICs, equipment and packaging. Clearly, though, the show is much smaller with fewer attendees, as compared to past years. Most of the big companies no longer have booths. Hardly any have press events or med... » read more

Pessimism, Optimism And Neuromorphic Computing


As I’ve been researching this series on neuromorphic computing, I’ve learned that there are two views of the field. One, which I’ll call the “optimist” view, often held by computer scientists and electrical engineers, focuses on the possibilities: self-driving cars. Homes that can learn their owners’ needs. Automated medical assistants. The other, the “pessimist” view, often hel... » read more

Toward Smarter Manufacturing


Semiconductor manufacturing is becoming increasingly competitive as significant investments in capital equipment are required to meet consumer demand for higher performing devices with greater functionality. To boost their competitiveness, chip makers are adopting Industry 4.0 manufacturing techniques to achieve higher levels of operational excellence. In this blog, I explain Industry 4.0, prov... » read more

The Future Of MEMS Design: Making MEMS Design More Like CMOS Design


MEMS-based component suppliers want to rapidly ramp their designs into high-volume production. This demand is driving MEMS suppliers to focus on ways to more efficiently re-use established process steps, stacks or technology platforms. To meet this need, we see the emergence of standard MEMS technology and design platforms similar to those used in CMOS design. The semiconductor industry and ... » read more

Mask Modeling In The EUV Era


D2S reviews the challenges of mask modeling in the EUV era, including the need for dose/shape separation and mid-range correction, and the impact of GPU acceleration. https://youtu.be/iVqkoVMbK4o » read more

Funding China’s 200mm Fabs


China’s ambitious plans to build a world-class semiconductor manufacturing supply chain domestically certainly has the industry’s attention. With over a dozen new 300mm fab announcements lately from Foundries, DRAM, 3D NAND, and as well as CMOS image sensor companies (either from international semiconductor makers or from indigenous players), China has launched a huge investment in wafer fa... » read more

Foundry Roadmaps: Real Solutions, Or Just Hedging?


Major semiconductor foundries have revealed their advanced technology roadmaps for the next few years. They’re all investing billions of dollars into the development of process technologies and packaging options. The number of alternatives has been described as ‘dizzying’. How can all the foundries remain profitable? How does the customer decide which ‘route’ to take? For the 2... » read more

Architecture First, Node Second


What a difference a node makes. A couple of rather important changes have occurred in the move from 16/14 to 10/7nm (aside from more confusing naming conventions). First, companies that require more transistors—processor companies such as [getentity id="22846" e_name="Intel"], AMD, [getentity id="22306" comment="IBM"] and [getentity id="22676" e_name="Qualcomm"]—have come to grips with t... » read more

Inside Chip R&D


Semiconductor Engineering sat down to discuss R&D challenges, EUV and other topics with Luc Van den hove, president and chief executive of Imec, an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Clearly, Moore’s Law is slowing down. The traditional process cadence is extending from 2 years to roughly 2.5 to 3 years. Yet, R&D is not slowing down, right? ... » read more

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