Will EUV Kill Multi-Patterning?


When I first began working on double-patterning (DP) tools back in late 2010, there was already talk that it might be a fruitless, or at a minimum, very short-lived project, as extreme ultraviolet (EUV) lithography was just around the corner and would make all multi-patterning (MP) obsolete. Well, as I begin my seventh year on this project, I can hear echoes of Mark Twain as clearly, the report... » read more

Using Automated Pattern Matching For SRAM Physical Verification


How often have you struggled to verify static random-access memory (SRAM) blocks in your design? And how often, no matter how much time you spend on them, do they end up causing manufacturing issues? Memory is a critical component in today’s SoC designs, often consuming 50% or more of the die area. SRAM blocks are typically assembled in a layout using a set of specific intellectual propert... » read more

Fill/Cut Self-Aligned Double-Patterning


By David Abercrombie, Rehab Ali, Ahmed Hamed-Fatehy, and Shetha Nolke Self-aligned double patterning (SADP) is an alternative double-patterning process to the traditional litho-etch-litho-etch (LELE) approach used in most advanced production nodes. The main difference between the two approaches is that in LELE, the layout is divided between two masks, and the second mask is aligned with resp... » read more

Creating An Accurate FEOL CMP Model


By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid For decades, semiconductor manufacturers have used chemical-mechanical polishing (CMP) as the primary technique for the smoothing and leveling (planarization) of dielectrics and metal layers. CMP modeling allows  design and manufacturing teams to find and fix potential planarization issues before the actual CMP process is applied to a ... » read more

The Pitfalls Of Auto-Stitching In Double-Patterning


Ever since the first double-pattern (DP) odd-cycle error ring was produced on a layout, designers have longed for a magic solution to solve it. Traditionally, the first approach to fixing an odd-cycle error was to move a polygon or a polygon edge to increase spacing to an adjoining polygon in the cycle. Alternatively, you could remove a polygon altogether, or split it into two pieces. All of th... » read more

Device Pin-Specific Property Extraction For Layout Simulation


As we work through the sub-20 nm design space, the interactions between and effects on devices that are near each other are becoming critical factors in achieving the desired electrical performance. Accurate extraction of device pin-specific properties for modelling these effects is essential to attaining design goals. LVS extraction challenges Layout vs. schematic (LVS) comparison tools prov... » read more

Colorless vs. Colored Double-Patterning Design Flows


Colored vs. Colorless double patterning design flows—do you know which one is best for your design? What options does your foundry allow? Do you debug one differently from the other? In this short video, I’ll demonstrate the differences between colored and colorless DP design flows, and explain the options and potential pitfalls of each approach. With a better understanding of how to design... » read more

Pattern Matching In Test And Yield Analysis


By Jonathan Muirhead and Geir Eide It’s no secret that a successful yield ramp directly impacts integrated circuit (IC) product cost and time-to-market. Tools and techniques that help companies ramp to volume faster, while also reducing process and design variability, can be the difference between profit and loss in a competitive market. And while pattern matching technology has been aroun... » read more

Pattern Matching in Design and Verification


Pattern matching (PM) was first introduced as the semiconductor industry began to shift from simple one-dimensional rule checks to the two-dimensional checks required by sub-resolution lithography. These rule checks proved far more complex to write, hard to code for fast runtimes, and difficult to debug. Incorporating an automated visual capture and compare process enabled designers to define t... » read more

ECOs and Multi-Patterning: It Can Be Done


By David Abercrombie and Alex Pearson A lot has been written and discussed about how to decompose (color) layouts for advanced process nodes that require multi­patterning (MP). However, one topic that has been sorely ignored is how to efficiently make changes to designs that are already colored, or even taped out and processed. We tend to act like all designs work out the first time through... » read more

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