Making Declarative Modeling Modular: Portable Stimulus Introduces Dynamic Constraints


Naturally, Accellera’s Portable Stimulus Standard (PSS) supports the powerful capabilities of advanced verification techniques that are well-known in the industry today, including object-oriented composition and constrained-random stimulus. But the PSS also supports a new constraint capability, called dynamic constraints. Dynamic constraints support the critical mission of the PSS by makin... » read more

Interface DRC Can Streamline Chip-Level Interface Physical Verification


In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning stages, blocks placed in the chip-level floorplan are usually still under development. Merging these incomplete blocks with the... » read more

How Automotive ICs Are Reshaping Semiconductor Test


The growth of a new IC market creates ripples along the entire supply chain. Today, we see the semiconductor industry reacting to the needs of the growing automotive IC market, including the development of new IC test tools and methods. The automotive IC market is far and away the fastest growing end-use market with 15% CAGR (according to IC Insights). It is also seeing many new players. Mar... » read more

A Reliability Baseline Is Essential For Today’s Complex IC Designs


Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ... » read more

Raising SoC Development Productivity With Portable Stimulus


The semiconductor industry has achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable design IP. The EDA industry has also achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable verification IP. A remaining bottleneck in the SoC development process stems from the inability to re... » read more

Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling


By Ron Press and Vidya Neerkundar The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, and there are more DFT integration steps than ever before. The traditional approaches to DFT work on huge designs pose problems of repeatability and reliability... » read more

How To Use CFD To Test And Analyze A Chip Package


By Prasad Tota and Robert Day Throughout the electronics industry, submicron feature size at the die level are driving package component sizes down to the design-rule level of the early technologies. Today’s integrated circuit (IC) package technology must deliver higher lead counts, reduced lead pitch, minimum footprint area, and significant volume reduction, which has led to semiconductor... » read more

Four Steps To Verifying An SSD Controller With Emulation


By Ben Whitehead and Paul Morrison Datacenters, cloud computing, the IoT, and all things electronic demand that huge amounts of data and information are stored securely and accessible anywhere at any time. This requirement is driving the adoption of new storage technologies. The capacity, size and performance of solid state drives (SSDs) make it a very interesting technology. It offers h... » read more

Get To Know The Gate-Level Power Aware Simulation


The post-synthesis gate-level netlist (GL-netlist) based PA simulation input requirements are mostly the same as RTL simulation. However, the design under verification here is the GL-netlist from synthesis, so logic gates from standard, MV and Macro cell Liberty libraries are already inserted or instantiated in the design. Hence power aware simulation (PA-SIM) at post-synthesis also requires Li... » read more

Collaborative Multi-Board System Design


Designing electronic systems has become measurably more complex during the past decade. Many of the products that are developed today are in-fact complex interconnected systems. Using the automotive market as an example, the first level of a system is an element; an individual component or sub-assembly that is designed to be part of a larger collaborating function. At the next level is the sub-... » read more

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