A Reliability Baseline Is Essential For Today’s Complex IC Designs


Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ... » read more

Raising SoC Development Productivity With Portable Stimulus


The semiconductor industry has achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable design IP. The EDA industry has also achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable verification IP. A remaining bottleneck in the SoC development process stems from the inability to re... » read more

Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling


By Ron Press and Vidya Neerkundar The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, and there are more DFT integration steps than ever before. The traditional approaches to DFT work on huge designs pose problems of repeatability and reliability... » read more

How To Use CFD To Test And Analyze A Chip Package


By Prasad Tota and Robert Day Throughout the electronics industry, submicron feature size at the die level are driving package component sizes down to the design-rule level of the early technologies. Today’s integrated circuit (IC) package technology must deliver higher lead counts, reduced lead pitch, minimum footprint area, and significant volume reduction, which has led to semiconductor... » read more

Four Steps To Verifying An SSD Controller With Emulation


By Ben Whitehead and Paul Morrison Datacenters, cloud computing, the IoT, and all things electronic demand that huge amounts of data and information are stored securely and accessible anywhere at any time. This requirement is driving the adoption of new storage technologies. The capacity, size and performance of solid state drives (SSDs) make it a very interesting technology. It offers h... » read more

Get To Know The Gate-Level Power Aware Simulation


The post-synthesis gate-level netlist (GL-netlist) based PA simulation input requirements are mostly the same as RTL simulation. However, the design under verification here is the GL-netlist from synthesis, so logic gates from standard, MV and Macro cell Liberty libraries are already inserted or instantiated in the design. Hence power aware simulation (PA-SIM) at post-synthesis also requires Li... » read more

Collaborative Multi-Board System Design


Designing electronic systems has become measurably more complex during the past decade. Many of the products that are developed today are in-fact complex interconnected systems. Using the automotive market as an example, the first level of a system is an element; an individual component or sub-assembly that is designed to be part of a larger collaborating function. At the next level is the sub-... » read more

Achieving Separation On Multiprocessor SoCs For Enhanced Safety And Security


As I read my colleague Andrew Caples’ article on The Blurring of Safety and Security for Embedded Devices, I immediately started to think of the Xilinx UltraScale+ MPSoC – as I have engaged with numerous customers about using this chip for both safety and security purposes, and the requirements for both areas are definitely starting to blur. I quickly realized a blog about the Xilinx... » read more

ON Semiconductor Meets AEC Challenges With Electrothermal Analysis


By Justin Yerger, ON Semiconductor, and Ahmed Eisawy, Mentor, a Siemens Business ON Semiconductor is a leading provider of products for automotive applications that follow the Automotive Electronics Council (AEC Q-100-012) requirements for reliability characterization of smart power devices. In particular, Automotive Smart FET driver ICs present verification challenges when verifying short c... » read more

Huawei Delivers Outstandingly Accurate Models


By John Parry, Mentor, a Siemens Business, and Yake Fang, Huawei Technologies Co., Ltd. Packaging high-performance multi-core IC devices used in communication applications is a key challenge for both manufacturers and system integrators. Traditionally a System-in-Package (SiP) has been taken, with chips mounted side-by-side, allowing differing semiconductor technologies to be mixed. More r... » read more

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