Fast Models, Cycle Models


There has been a lot of coverage since the launch of new CPU and graphics cores at Computex 2017, including some information about early software development. The public announcement of new ARM IP is a milestone for ARM Models because it means we can now talk about available models and share additional information about the new IP. ARM Fast Models and Cycle Models enable virtual prototyping ... » read more

Open-Source NFV


The OPNFV Summit in Beijing earlier this month brought together developers, end users, and other communities all working to advance open source Network Functions Virtualization (NFV). What's new is an effort to make NFV more efficient. A highlight of the event was the announcement of an exciting new platform for accelerating NFV software development, the “NFV PicoPod”. Developed in coll... » read more

Capturing The Future, Frame By Frame


A lot has changed over the past year, and more changes are on the way. Consider what's happening in API tracing. All of the functions from the Vulkan specification can be traced correctly in MGD. This means that you will be able to see exactly what Vulkan calls your application makes and in what order. You will also be able to see what threads each of these function calls occur in. Figu... » read more

Ubiquitous AI


We have witnessed an amazing expansion of compute power over the past four years. Go inside the numbers of the recent 100 billion ARM-based chips milestone and you will see that 50 billion were shipped by our partners from 2013 to 2017, which demonstrates the industry’s insatiable demand for more compute. Even more extraordinary is that we expect our partners to ship the next 100 billion ARM-... » read more

Constructing The Pillars Of The ARM HPC Ecosystem


In talking with HPC users at SC15 following the announcement of the OpenHPC project, I consistently heard that while they valued having a common open source framework covering a baseline set of HPC codes, they wanted to see more than one chip architecture represented. This is important when you consider that many HPC users are focused on getting to exascale computing for future supercomputer de... » read more

A Security Foundation For Billions Of Devices


October 19, 2004 was a date like any other, and will probably not mean much to most people. However, if you are part of the Embedded community, that precise date was transformational for the microcontroller (MCU) industry. It was the day that ARM announced the first Cortex-M processor, bringing the advantages of a common architecture to the microcontroller market. Embedded developers quickly... » read more

Do More, Earlier


The ARM Cortex-R52 processor is the most advanced processor for functional safety and the first implementation of the ARMv8-R architecture. Along with the announcement of the Cortex-R52, ARM offers a number of development tools to help partners speed up their path to market. This is especially helpful for a new architecture which highlights software separation for safety and security. This arti... » read more

New Ways To Scale Performance


Immense amounts of data are being collected today in areas such as meteorology, geology, astronomy, quantum physics, fluid dynamics, and pharmaceutical research. Exascale computing (the execution of a billion billion floating point operations, or exaFLOPs, per second) is the target that many HPC systems aspire to over the next 5 to 10 years. In addition, advances in data analytics and areas su... » read more

Why Instrumentation Isn’t Optional


When writing code it is often useful to add informational statements that give an insight into control flow and data management as well as aiding in observation of the actual code at runtime. As such, instrumentation is an important component of code running on a live system. The proliferation of "printf" debug statements, whereby data is output to a console, is testament to this. Sending te... » read more

Digging Into Trace Data


In previous blogs we covered an introduction to System Trace Macrocell (STM) concepts and terminology, and the STM Programmers' model with an example of how to generate efficient trace data. Once the STM is generating a trace stream, we may wish to view it within our Debugger. DS-5 implements an "Events View," which serves this purpose. Configuring your target First, it is necessary to... » read more

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