Avoiding Traffic Jams In SoC Design


While sitting in a traffic jam on the way to work, I realized that the sheer volume of vehicles on the road exceeds the capacity originally planned for by civil engineers, when highways first hit the drawing boards 50 or 60 years ago. It dawned on me that there is a parallel to today’s System-on-Chip design—engineers are struggling to close timing on the interconnect during the back-end pla... » read more

Reducing Latency In ADAS SoC Design Enhances QoS For Digital Mirroring


The state-of-the-art of Advanced Driver Assistance Systems (ADAS) is quickly changing, and ADAS chip engineers are finding that on-chip quality-of-service (QoS) is becoming a system-level constraint on ADAS performance. Designers need innovative approaches to address these issues, which is why Dream Chip Technologies highlighted one such method in a recent presentation. Dream Chip Technologi... » read more

Toward Better Accelerators


In the not-too-distant past, the standard mobile application processor architecture was the predominant one used for most System-on-Chip (SoC) designs, but that is rapidly changing as new systems and applications emerge in the post-mobile computing era. New requirements for autonomous driving are motivating technology innovations: Visual processing, deep neural networks and machine learning pla... » read more

ISO 26262 Functional Safety Training Resources


The automobile has taken over the mobile phone’s pole position as the driver of new semiconductor technologies, like machine learning and vision processing. As a result, many electrical engineers in the semiconductor industry are finding themselves in a state of transition where their current skills, education, and experience are not sufficient for them to achieve the kind of role they would ... » read more

Early Power Modeling Using SystemC And TSMC System-PPA


Power consumption is often more important than performance in today’s SoC designs because of battery size and power dissipation limitations. The dilemma is that the most leverage available to optimize power consumption is at the architectural design stage, but there often is not enough information available early enough to make accurate power decisions. On the performance side, SystemC mod... » read more

All You Need Is Cache (Coherency) To Scale Next-Gen SoC Performance


Life on the SoC performance front remains a withering battle sometimes, because things can seem fairly bleak. As transistor scaling becomes more expensive below 10-nanometer feature sizes, every day it becomes harder to double performance every 18-months or so and stay competitive. Nowhere is the pain of this battle more acute than in consumer and automotive systems, where low cost is the key t... » read more

USDOT Smart City Challenge: Columbus Drives Future of Automotive Semiconductor Development


The Smart City Challenge will be an accelerant of automotive semiconductor innovation. The U.S. Department of Transportation has chosen Columbus as the winner of the Smart City Challenge, entitling Ohio’s capital city to $40 million U.S. government funding, along with $10M from Paul Allen’s Vulcan investment firm, and $90M that Columbus raised from private partners, to create a fully integr... » read more

Why Is Semiconductor Schedule Predictability Boring?


Why is it not sexy to talk about the manageability of system-on-chip (SoC) projects? As an IP vendor, we are constantly bombarded with questions about how our technology can enhance performance, reduce latency, and lower power consumption. At the same time, reducing cost and time to market for the SoC design conflict with these requirements, even though they rank right up there among the top en... » read more

CPU, GPU or … VPU?


Where is the semiconductor industry going in the post-smartphone era? What trends are going to shape next-generation applications and SoC development? Just by walking around the CES show floor this year, I would say advanced visual processing technology is the horse to put money on. It was everywhere, from ADAS systems, drones, to GoPro cameras, IP cameras with embedded facial recognition, m... » read more

How To Reduce Timing Closure Headaches


As chips have become more complex, timing closure has provided some of the most vexing challenges facing design engineers today. This step requires an increasing amount of time to complete and adds significantly to design costs and back-end schedule risks. Wire delay dominates transistor switching delay Building high-performance modern CPUs involves pipelining to achieve high frequencies. I... » read more

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