Semicon West Lithography Report

OK, I have to admit this right off:  I didn’t go to Semicon West (held two weeks ago in San Francisco).  I try never to go to Semicon West (I’ve been twice in the last 30 years, both times against my will).  Why should I go?  To listen to the latest marketing messages and company spin?  To see a few technical talks that are way too light on the technical, but still full of talk?  I do... » read more

SPIE Advanced Lithography 2013 – day 2

There were some great papers at AL on Tuesday.  Here are some of my favorites.  Peter Trefonas of Dow created a photosensitive block copolymer using a class of molecules called bottle brush polymers.  This very early work nonetheless exhibited very good results – close to 20 nm resolution (e-beam litho) with nearly the first bottle of stuff they mixed up.  The idea is simple:  marry the ... » read more

SPIE Advanced Lithography 2013 – day 4

The final day of the Advanced Lithography Symposium contains what is commonly referred to as the “tool” sessions, where tool makers give updates on their latest and greatest products.  As such it tends to have the most commercial presentations, with all the problems that come with commercial pressures.  For the EUV conference it is also the day where technology cheerleading, and skepticis... » read more

SPIE Advanced Lithography 2013 – day 3

Wednesday was, for me, a busy day since I had two talks to give.  The first was the opening keynote talk at the Design for Manufacturability (DFM) conference entitled “The future of lithography and its impact on design”.  The take-home message was that lithography would become less critical to the success of the industry, and that materials, device architecture, and design would be the ke... » read more

SPIE Advanced Lithography 2013 – day 1

Day 1 of the SPIE Advanced Lithography Symposium began, as always, with the plenary session.  Bill Arnold, former lithography manager at AMD and now CTO at ASML, gave a “state of the union” address – he is this year’s SPIE president.  (Congratulations, Bill – I voted for you!)  The 10th Zernike Award for achievements in microlithography went to Dave Markle, a well-deserved honor (f... » read more

SPIE Advanced Lithography 2013 – day 0

Welcome to San Jose and the beginning of the Advanced Lithography Symposium.  The last year seemed to zip by in hurry, and it was an interesting one.  The lithography year 2012 was dominated by two big stories:  progress in directed self assembly (DSA) and lack of progress in Extreme Ultraviolet (EUV) lithography.  I’m anxious to hear the progress reports for each this week.  For EUV, de... » read more

ASML to Buy Cymer

"We have experienced some delay in EUV, basically caused by delays in developing the light source", said Peter Wennink, ASML's financial chief. With that understatement, ASML succinctly explained its rationale for offering $2.6B in cash (25%) and stock (75%) to buy San Diego-based Cymer, the leading developer of EUV sources.  Over the last year, ASML has sent about 500 of their engineers to... » read more

Why the Big Players Like 450mm Wafers

The reason semiconductor manufacturers like the idea of 450-mm wafers is easy to understand:  bigger wafers should lower the per-chip cost of manufacturing.  But as I mentioned in my last post, this per-chip cost advantage doesn’t apply to lithography.  Each time a wafer size is increased, only the non-litho (per-chip) costs go down, and so lithography costs take up a bigger portion of the... » read more

Why 450mm wafers?

Why is 450-mm development so important to Intel (and Samsung and TSMC)? A few years ago, Intel and TSMC began heavily promoting the need for a transition from the current standard silicon wafer size, 300 mm, to the new 450-mm wafers.  While many have worked on 450-mm standards and technology for years, it is only recently that the larger wafer has received enough attention and support (not ... » read more

The Resolution Limit of Hard Drive Manufacturing

In lithography, pushing the limits of resolution is what we do.  These efforts tend to get a lot of press.  After all, the IC technology nodes are named after the smallest nominal dimensions printed with lithography (though the marketing folks who decide whether the next generation will be called the 16-nm or 14-nm node don’t care much about the opinions of lithographers).  And the looming... » read more

← Older posts