Performance Increasingly Tied To I/O


Speeding up input and output is becoming a cornerstone for improving performance and lowering power in SoCs and ASICs, particularly as scaling processors and adding more cores produce diminishing returns. While processors of all types continue to improve, the rate of improvement is slowing at each new node. Obtaining the expected 30% to 50% boost in performance and lower power no longer can ... » read more

TSMC: 10nm To Be Greater Than 10% Of 2017 Wafer Revenue


TSMC’s financial results for the 4th Quarter of 2016 were released on January 11, 2017 (PST) and showed that year-over-year fourth quarter revenue increased 28.8% and simultaneously net income and diluted EPS both increased 37.6%.  In U.S. dollars, TSMC’s fourth quarter revenue was $8.25 billion. TSMC's CFO, Ms. Lora Ho, reported that 2016 was a good year for TSMC and that the company set ... » read more

Power/Performance Bits: Jan. 17


Creating magnets with electricity Researchers at the SLAC National Accelerator Laboratory, Korea Advanced Institute of Science and Technology (KAIST), Korea Institute of Materials Science, Pohang University of Science and Technology, Max Planck Institute, and the University of New South Wales drew magnetic squares in a nonmagnetic material with an electrified pen and then "read" this magneti... » read more

Choosing Power-Saving Techniques


Engineers have come up with a long list of ways to save power in chip and system designs, but there are few rules to determine which approaches work best for any given design. There is widespread confusion about what techniques should be used where, which IP or subsystem is best, and how everything should be packaged together. The choices include everything from the proper level of clock and... » read more

Border Tax Shakeup


A border tax is the talk of the financial world. While this has clear implications for car manufacturers, where it's rather easy to tell where parts such an engine block or a braking system were manufactured, it's far less tangible when it comes to electronics in general, and semiconductors in particular. In a complex SoC, IP can be developed in more than one country, and multinational techn... » read more

What’s Missing In Deep Learning?


It is impossible today to be unaware of deep learning/machine learning/neural networks -- even if what it all entails is not even clear yet. Someone who is intimately familiar with this area, and has some thoughts on this is Chris Rowen, founder of Tensilica (now part of Cadence), who is now a self-described hat juggler. He is still active Cadence several days a month, working technically on... » read more

When DDR DRAM Is Right For Automotive Systems


Most of the processors contained within automobiles are relatively small and with modest memory requirements that can be served by SRAM and non-volatile memory. The type of computing, image processing, and graphics displays that are possible with a more powerful CPU connected to DRAM have largely been restricted to the non-safety-critical infotainment system in the vehicle – until now. Advanc... » read more

The Challenges Of Designing 28G And 56G SerDes IP


The industry move to 56 Gbps PAM4 is undoubtedly one of the greatest challenges currently facing SerDes IP designers and their customers. To begin with, shifting to 56 Gbps PAM4 immediately causes a loss of 9 dB. While the baud rate is 28 Gbaud, there are now three eyes stacked on top of each other. Nevertheless, there is still demand for 35+ dB reach. This is a significant challenge which requ... » read more

The Multiplier And The Singularity


In 1993, Vernor Vinge, a computer scientist and science fiction writer, first described an event called the Singularity—the point when machine intelligence matches and then surpasses human intelligence. And since then, top scientists, engineers and futurists have been asking just how far away we are from that event. In 2006, Ray Kurzweil published a book, "The Singularity is Near," in whic... » read more

7nm Design Success Necessitates A Multi-Physics Approach


Whether you are designing an energy efficient mobile device, or an ADAS platform with stringent reliability requirements, or a high performance enterprise networking system, chips fabricated on advanced technologies such as 7-nanometer (nm) process and 2.5/3D or wafer level packaging can provide several advantages. Designs using these technologies consume less power while delivering higher thro... » read more

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