Power/Performance Bits: Mar. 19


Explainable AI Researchers from Technische Universität Berlin (TU Berlin), Fraunhofer Heinrich Hertz Institute (HHI), and Singapore University of Technology and Design (SUTD) propose a pair of algorithms to help determine how AI systems reach their conclusions. Explainable AI is an important step towards practical applications, argued Klaus-Robert Müller, Professor for Machine Learning at... » read more

The Growing Challenge Of Thermal Guard-Banding


Guard-banding for heat is becoming more difficult as chips are used across a variety of new and existing applications, forcing chipmakers to architect their way through increasingly complex interactions. Chips are designed to operate at certain temperatures, and it is common practice to develop designs with some margin to ensure correct functionality and performance throughout the operat... » read more

Power Budgets At 3nm And Beyond


There is high confidence that digital logic will continue to shrink at least to 3nm, and possibly down to 1.5nm. Each of those will require significant changes in how design teams approach power. This is somewhat evolutionary for most chipmakers. Five years ago there were fewer than a handful of power experts in most large organizations. Today, everyone deals with power in one way or another... » read more

Using Less Power At The Same Node


Going to the next node has been the most effective way to reduce power, but that is no longer true or desirable for a growing percentage of the semiconductor industry. So the big question now is how to reduce power while maintaining the same node size. After understanding how the power is used, both chip designers and fabs have techniques available to reduce power consumption. Fabs are makin... » read more

IC Test: Doing It At The Right Place At The Right Time


In the real world, we are slaves to our environment. The decisions we make are dependent on the resources available at any given time. In school, I remember coming up with a binary decision diagram (BDD) variable-ordering algorithm that relied on partial BDDs. Was that the best algorithm to determine the variable ordering of a BDD for a design? Probably not. However, it was easy to do as a coll... » read more

Trends In FPGA Verification Effort And Adoption: The 2018 Wilson Research Group Functional Verification Study


As contributors and pioneers in the digital revolution, we are often so busy creating and innovating that we are compelled to focus on the trees, never mind the forest. But as we are all aware, the more we know about the bigger picture, context, historical and projected trends, or simply how other people are doing the same thing, the more efficiently and successfully we can do our jobs. Prov... » read more

Memory Tradeoffs Intensify in AI, Automotive Applications


The push to do more processing at the edge is putting a strain on memory design, use models and configurations, leading to some complex tradeoffs in designs across a variety of markets. The problem is these architectures are evolving alongside these new markets, and it isn't always clear how data will move across these chips, between devices, and between systems. Chip architectures are becom... » read more

Timing Is Of The Essence


Today's advanced 16/7nm system-on-chips (SoCs) are faced with increased variation as they push for lower power. While the sizes of the transistors continue to shrink following Moore's Law, the threshold voltages fail to scale. This causes wide timing variability leading to timing closure difficulties, design re-spins and poor functional yield. Learn how ANSYS Path FX with its unique variatio... » read more

The Importance Of Using The Right DDR SDRAM Memory


Selecting the right memory technology is often the most critical decision for achieving the optimal system performance. Designers continue to add more cores and functionality to their SoCs; however, increasing performance while keeping power consumption low and silicon footprint small remains a vital goal. DDR SDRAMs, DRAMs in short, meet these memory requirements by offering a dense, high-perf... » read more

GDDR6: Signal Integrity Challenges For Automotive Systems


Signal integrity (SI) is at the forefront of SoC and system designers’ thinking as they plan for upcoming high-speed GDDR6 DRAM and PHY implementations for automotive and advanced driver assistance system (ADAS) applications. Rambus and its partners are closely looking at how GDDR6’s 16 gigabit per second speed at each pin affects signal integrity given the cost and system constraints for a... » read more

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