Getting A Handle On RTL X-Verification Challenges

The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout.  Some engineers point out that we have always had to deal with X’s and nothing has really changed. In fact, today’s SoC employ different power management schemes that wake-up or suspend IP.  As any designer knows, when powering ... » read more

Design And Verification Survey Results

Previously I have blogged about the verification surveys that Real Intent runs at tradeshows throughout the year.  We find it useful to track trends in tool needs and reveal what are the pain points designers are feeling.  I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing re-spins. This year, I would like ... » read more

Billion-Gate Signoff

At last year’s Design and Verification Conference in San Jose, Real Intent had a tutorial session on “Pre-Simulation Verification for RTL Sign-Off.” This was a start of conversation in the industry that we have seen grow through DAC 2013 in Austin, and which is getting louder each day. Verification companies are now talking about crossing the billion-gate threshold and what can be done to... » read more

Key Developments In 2013 And Crystal Ball Predictions For 2014

There were a number of key developments in 2013 that stood out for me that I think would of interest to the Semiconductor Engineering audience:  We are now in the world of 8-core processors. Both the new Xbox One and the Sony PS4 sport 8-core AMD CPUs. And MediaTek has announced the MT6592, the first 8-core cell-phone chip that uses ARM A-7 processors running simultaneously at 2GHz. I know... » read more

The Race For Better Verification

SoC verification is gearing up for renewed competition among the big vendors and verification-only companies like Real Intent. They are delivering their next-generation SoC verification suites with a focus on specific areas of concern. Clock-domain crossing, X-verification and reset optimization, SDC correctness and consistency, are some of the areas that are receiving dedicated RTL analysis us... » read more

Are Designers’ X-Analysis Needs Different From Verification Engineers?

The propagation of unknown (X) states has become a more pressing issue with the move toward billion-gate SoC designs. Besides the sheer complexity of these designs, the common use of complex power management schemes increase the likelihood of an unknown ‘X’ state in the design translating into a functional bug in the final chip. This article describes a methodology that enables design an... » read more

A Night to Remember: EDA Back to the Future

I had the pleasure to attend the EDA: Back to the Future event at the Computer History Museum on Oct. 16.   There were over 230 guests to raise money for the EDA Oral History Project at the Museum.   There were industry luminaries honored at the event, and I did red carpet interviews with many of them as they arrived including Joe Costello, Simon Segars, and Penny Herscher.  As I did the i... » read more

Best-In-Class Tools Lead To Best-In-Class Design?

Today’s systems on chip (SoC) are deeply complex in new ways. A dozen or so years ago, a state-of-the-art processor such as the Intel Pentium 4 used 42 million transistors, was built on a 180nm process and relied upon discrete chips to handle its system interfaces. Jump forward, and the Intel Xeon Phi processor that Intel introduced in 2012 uses 5 billion transistors and is built on a 22nm pr... » read more

Does SoC Signoff Mean More Than RTL?

As the cost of failure continues to rise, SoC engineers see the growing importance of ensuring their work is as correct as possible as soon as possible in the design process. They cannot afford to carry errors forward from one stage to the next, where their impact grows while their causes become more obscured. This requirement is driving the shift in design exploration and handoff to the reg... » read more

Unknown Signoff

In last month’s blog, Pranav Ashar, CTO at [getentity id="22416" e_name="Real Intent"], pointed out that the management of unknowns (X’s) in simulation has become a separate verification concern of signoff proportions. Modern power management schemes affect how designs are reset (start). X management and reset analysis are interrelated because many of the X’s in simulation come from unini... » read more

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