Learn From The Experts


I visited SNUG Silicon Valley last week. This annual Synopsys User Group event at the Santa Clara Convention Center is always a good way to get in touch with the end users of various EDA products. I attended the technical track with experts from ARM, NVIDIA, Intel and Synopsys, who talked about their experience in accelerating software development, hardware verification and system validation... » read more

Custom Chip Verification Issues Grow


With the transition to finFETs, design conditions have grown more intense. They now include a wider PVT range and less headroom. As a result, electronic systems for applications such as mobile, consumer, and automotive increasingly are becoming more difficult to design due to the exacting performance requirements of these applications. This is particularly evident in custom design, including... » read more

Blog Review: March 29


In a video, Cadence's Megha Daga introduces how convolutional neural networks identify objects and the wide range of applications for the technology. Mentor's Ron Press proposes a way to take advantage of hierarchical DFT features, even if a design wasn't designed for it. Synopsys' Robert Vamosi shares highlights of the RAND Corporation's extensive report examining zero day vulnerabilitie... » read more

System Bits: March 28


Automating biology experiments with adapted Lego kit To bring more of the features of modern biology labs — that often use robotic assemblies to drop precise amounts of fluids into experimental containers — to students and teachers, Stanford University researchers have shown how an off-the-shelf Lego kit can be modified to create inexpensive automated systems to do this in clubs or classro... » read more

EDA Revenue Up 18.9%


Marking the highest quarterly revenue increase in 5 years, the Electronic System Design (ESD) Alliance reported today that EDA revenue increased 18.9 percent for Q4 2016 to $2.455 billion, compared to $2.0645 billion in Q4 2015. The four-quarters moving average was up by 9.2%, which compares the most recent four quarters to the prior four quarters. Walden C. Rhines, board sponsor for the ESD... » read more

Supporting CPUs Plus FPGAs


While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

Biz Talk: ASICs


eSilicon CEO [getperson id="11145" comment="Jack Harding"] talks about the future of scaling, advanced packaging, the next big things—automotive, deep learning and virtual reality—and the need for security. [youtube vid=leO8gABABqk]   Related Stories Executive Insight: Jack Harding (Aug 2016) eSilicon’s CEO looks at industry consolidation, competition, China’s impact, an... » read more

The Week In Review: Design


Tools Synopsys revealed a comprehensive low power reference kit for design and verification based on a bitcoin mining SoC design. The kit is designed to help accelerate deployment of a Unified Power Format (UPF)-based hierarchical design methodology and as a learning vehicle for the complete Synopsys low power flow. Space Codesign introduced the latest version of its simulation environmen... » read more

Optimal Memory Strategies: Where HBM2 Fits


How are you going to build your next big product? Whether it’s in the networking, wireless, mobile or computing market, you are now increasing the functionality of your product. It needs to be able to do many tasks – fast, at low power, and pack as much functionality into the tiniest area for cost effectiveness. What does this mean for the embedded memory content? It is growing rapidly. ... » read more

When Will It Be Done?


Design teams have done remarkably well in getting chips out the door on time, despite growing complexity at each new node and an increase in the number of features and IP blocks that need to be integrated into designs. There has been plenty of grumbling, along with dire warnings about the future of Moore's Law and the impact of industry consolidation. The reality, though, is that the volume ... » read more

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