Move Data Or Process In Place?


Chip architectures, and even local system architectures, long have found that the best way to improve total system performance and power consumption is to move memory as close to processors as possible. This has led to cache architectures and memories that are tuned for those architectures, as discussed in part 1 of this article. But there are several tacit assumptions made in these architectur... » read more

The Week In Review: Design


Tools Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM. Pulsic added new features to its Unity Bus Planner for planning... » read more

Blog Review: Nov. 15


Cadence's Paul McLellan shares highlights from the Jasper User Group, including what to do when formal is not converging on a proof and formal in use at Arm. Synopsys' Anders Nordstrom explains how formal can verify SoC interconnects and get you from San Jose to Austin. Mentor's Jeff Miller argues that intelligent sensors are the basic building block for the IoT, and the market is growing... » read more

System Bits: Nov. 14


Tracking cyber attacks According to Georgia Tech, assessing the extent and impact of network or computer system attacks has been largely a time-consuming manual process, until now since a new software system being developed by cybersecurity researchers here will largely automate that process, allowing investigators to quickly and accurately pinpoint how intruders entered the network, what data... » read more

The Week In Review: Design


IP Cryptographic flaws have been discovered in the IEEE P1735 standard for encrypting IP and managing access rights. A team from the University of Florida found "a surprising number of cryptographic mistakes in the standard. In the most egregious cases, these mistakes enable attack vectors that allow us to recover the entire underlying plaintext IP." The researchers warn that an adversary coul... » read more

Blog Review: Nov. 8


Synopsys' Eric Huang digs in to what's new with USB 3.2 and what's achieved by preserving the existing PHY signaling speeds. In a video, Mentor's Colin Walls provides tips on how to write debuggable and maintainable embedded code. Cadence's Paul McLellan listens in on a talk by Andrew Kahng of UC San Diego on the problem of scaling and why machine learning can improve EDA tools. Rambus... » read more

System Bits: Nov. 7


Exposing logic errors in deep neural networks In a new approach meant to brings transparency to self-driving cars and other self-taught systems, researchers at Columbia and Lehigh universities have come up with a way to automatically error-check the thousands to millions of neurons in a deep learning neural network. Their tool — DeepXplore — feeds confusing, real-world inputs into the ... » read more

The Week In Review: Design


M&A Synopsys will acquire Black Duck Software, a provider of software for securing and managing open source software. Synopsys already has a stake in this area from its Coverity acquisition in 2014, which it has been using to analyze security practices in open source software. Founded in 2003 and headquartered in Massachusetts, Black Duck's products automate the process of identifying and ... » read more

Blog Review: Nov. 1


Mentor's Nitin Bhagwath continues digging into DDR timing with a look at the clock-to-DQS requirement at the DRAM and how "write-leveling" is used to solve layout issues caused by the requirement. Synopsys' Dipesh Handa checks out what's new in the MIPI CSI-2 v2.0 specification that opens it up to new imaging and vision applications, including IoT and automotive. Cadence's Ken Willis delv... » read more

Which Verification Engine?


Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

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