Dealing With System-Level Power


Analyzing and managing power at the system level is becoming more difficult and more important—and slow to catch on. There are several reasons for this. First, design automation tools have lagged behind an understanding of what needs to be done. Second, modeling languages and standards are still in flux, and what exists today is considered inadequate. And third, while system-level power ha... » read more

IoT Myth Busting


The [getkc id="76" comment="Internet of Things"] (IoT) means many things to a large number of people, but one thing is clear—every discussion involving the IoT invariably includes some rather dramatic growth predictions for how many connected devices will be sold and who will be the primary beneficiaries. While that data helps spice up speeches, and typically gets people to read and quote ... » read more

Is The IP Industry Healthy?


The semiconductor industry has been through many changes, each designed to reduce the total cost associated with the design and manufacture of chips. Twenty years ago, most companies had their own fabs and designed all of the circuitry on each chip. Today, only a handful of companies still own a fab and outsourcing design, in the form of intellectual property ([getkc id="43" kc_name="IP"]), has... » read more

Modeling On-Chip Variation At 10/7nm


Simulation, a workhorse tool for semiconductor design, is running out of steam at 10/7nm. It is falling behind on chips with huge gate counts and an enormous number of possible interactions between all the different functions that are being crammed onto a die. At simulation's root is some form of SPICE, which has served as its underpinnings ever since SPICE was first published 44 years ago. ... » read more

Transient Power Problems Rising


Transient power is becoming much more problematic at 10/7nm, adding yet another level of complexity for design teams already wrestling with power issues caused by leakage, a variety of power management techniques to control dynamic power, and leakage current. At each new node there is less headroom for engineering teams to address these problems, and more likelihood that what they do in one ... » read more

Safety Plus Security: A New Challenge


Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

Hardware/Software Tipping Point


It doesn't matter if you believe [getkc id="74" comment="Moore's Law"] has ended or is just slowing down. It is becoming very clear that design in the future will be significant different than it is today. Moore's law allowed the semiconductor industry to reuse design blocks from previous designs, and these were helped along by a new technology node—even if it was a sub-optimal solution. I... » read more

Maintaining Power Profiles At 10/7nm


Understanding power consumption in detail is now a must-have of electronic design at 10nm and below, putting more pressure on SoC verification to ensure a device not only works, but meets the power budget. As part of this, the complete system must be run in a realistic manner — at the system-level — when the design and verification teams are looking at the effects of power during hardwar... » read more

Power Challenges At 10nm And Below


Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

Closing The Loop On Power Optimization


[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more

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