Massively Parallel Electrically Aware Design

In-design verification is opening new opportunities to shorten design cycles and maximize circuit performance. Whereas physical verification has traditionally required a tradeoff between accuracy and performance for larger designs, recent advances in large-scale distributed computing may offer an alternative. Cloud infrastructure needs are pushing the industry toward larger multi-core server ar... » read more

What Is Fuzzing?

Fuzzing is an excellent technique for locating vulnerabilities in software. The basic premise is to deliver intentionally malformed input to target software and detect failure. A complete fuzzer has three components. A poet creates the malformed inputs or test cases.A courier delivers test cases to the target software. Finally, an oracle detects target failures. Different fuzzing techniques ... » read more

Coherency: The New Normal In SoCs

We are not far from devices each handling 100 teraflops of compute, billions of pixels of display, hundreds of gigabits of connectivity, and terabytes of storage. Compared with current state-of-the-art mobile SoCs, these are increases of one or two orders of magnitude — at similar or preferably lower power consumption. SoC design is changing to meet this challenge. Multicore architecture i... » read more

Xilinx Zynq-based Development Platform for ADAS

ADAS is an essential step between initial DA (Driver Assistance) systems and fully autonomous cars capable of driving without human guidance. Aldec provides an FPGA-based development platform powered by Xilinx Zynq-7000 SoC/FPGA heterogeneous technology, as well as a set of ADAS-class reference designs for rapid development of current and next-generation ADAS solutions for the automotive market... » read more

Find The Best IP For You

It can be quite challenging and time consuming to find the right semiconductor IP for your project. You’ve got to find IP that does not consume too much power, meets your performance target, has the lowest leakage when your product goes on standby, and last but not least, IP that occupies the least amount of expensive real estate on your chip. How can you accomplish such a task without having... » read more

Is This a Manufacturing Revolution?

In this eighth and final part of this series, we take a look at the risk that changes bring to quality control and test, and we discuss the potential effects on the future of moving to Industry 4.0. To read more, click here. » read more

Application Of Overlay Modeling And Control With Zernike Polynomials In An HVM Environment

By JawWuk Ju, MinGyu Kim and JuHan Lee of SK Hynix; Jeremy Nabeth, John C. Robinson and Bill Pierson of KLA-Tencor; and Sanghuck Jeon and Hoyoung Heo of KLA-Tencor Korea. Abstract Shrinking technology nodes and smaller process margins require improved photolithography overlay control. Generally, overlay measurement results are modeled with Cartesian polynomial functions for both intra-field... » read more

Testing the Big Bang of Smart Devices

Thanks to the proliferation of smart devices in the Internet of Things (IoT), it’s a circumstance not unlike the overwhelming sense of wonder and bewilderment that ancient Greek astronomer Ptolemy must have felt when gazing up at a sky full of stars on a clear winter’s night, trying to rationalize the vast tableau before him. But just as we wouldn’t critique early astronomers and philo... » read more

A Novel Approach To Dummy Fill For Analog Designs Using Calibre SmartFill

With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

FinFET Front-End-of-Line (FEOL) Process Integration With SEMulator3D

Purely geometric scaling of transistors ended around the 90-nanometer (nm) era. Since then, most power/performance and area/cost improvements have come from structural and material innovations. Silicon-on-Insulator (SOI), first “partially depleted” and more recently “fully depleted” as well as embedded stressors, High-K / Metal-Gate (HKMG) and now FinFETs are examples of technology inno... » read more

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