Optimizing DRAM Development Using Directed Self-Assembly (DSA)


Directed Self-Assembly (DSA) is an emerging technology that has the ability to substantially improve lithographic manufacturing of semiconductor devices. In DSA, copolymer materials self-assemble to form nanoscale resolution patterns on the semiconductor substrate. DSA technologies hold the promise to substantially improve the resolution of existing lithographic processes (such as self-aligned ... » read more

The Path To (Virtually) Zero Defective Parts Per Million


Despite thorough wafer and package testing, a small number of defective ICs can make their way into systems. These test "escapes" often return as field failures, increasing costs and eroding profit margins. They can also present a hazard if deployed in safety-critical systems, which is why companies purchasing semiconductors for automotive, medical, or aerospace applications often demand a zero... » read more

IP Qualification with Oasys-RTL


With increasing design sizes and complexities, the use of IP (intellectual property) as basic building blocks for better SoC design is also increasing. This paper presents the challenges faced during IP integration at the SoC level and what can be done to mitigate those risks during IP development. Mentor’s Oasys-RTL RTL floorplanning and physical synthesis tool offers a unique IP qualificati... » read more

Massive SoC Designs Open Doors To New Era In Simulation


As system-on-chip (SoC) designs have grown in size, simulation technologies have had to evolve dramatically to keep pace. We’re now at an inflection point where both speed and capacity are essential and new simulation technologies are needed to meet the demands. In this paper, we’ll discuss how simulation has evolved and examine how new technologies such as the Cadence RocketSimTM Parallel ... » read more

Electrothermal Mechanical Stress Reference Design Flow For Printed Circuit Boards And Electronic Packages


This paper presents a reference design flow for solving the electrical, thermal and mechanical challenges of a printed circuit board (PCB) using simulation tools from ANSYS. This approach can be utilized for all electrical CAD (ECAD) types such as IC packages, touch panel displays, and glass and silicon interposers. The authors followed this reference design flow for analyzing a PCB virtual pro... » read more

How Formal Reduces Fault Analysis For ISO 26262


The ISO 26262 standard defines straightforward metrics for evaluating the “safeness” of a design by defining safety goals, safety mechanisms, and fault metrics. However, determining those metrics is difficult. Unlike simulation where it is never known if the design has been simulated enough or given enough input, formal verification conclusively determines if faults are safe or not, making ... » read more

Connected Car Driving Change In Defect Detection


Automotive product design is rapidly evolving and the magnitude and pace of change facing engineering organizations is challenging incumbent processes and resources, especially in the area of software design. While connected cars are not new, the frequency and depth to which the industry is embracing this dynamic is accelerating. Software has emerged as a primary vehicle for innovation and diff... » read more

Advanced 3D eWLB-PoP Technology


The emergence and evolution of any package technology is driven by market trends as experienced by the end application. With the maturation of the mobile market, the trends for Smartphone and other mobile devices are more than ever for lower cost. Meanwhile, a higher degree of functionality and performance, thinner profile, and longer battery life are some of the additional market drivers seen ... » read more

Outlier Detection


With increasing focus on quality and reliability across all segments beyond just automotive, medical and mil-aero, it is more critical than ever for companies to leverage every byte of test data at their disposal to ensure that they deliver the lowest possible DPPM (defective parts per million) rates to their customers. Semiconductor manufacturing operations now generate up to 100TB of test ... » read more

Implementing Fan-Out Wafer-Level Packaging with Mentor Graphics


Fan-out wafer-level packaging (FOWLP) is a new high-density packaging technology that is rapidly gaining popularity. What is it? Who needs it? How do you take advantage of it? What limitations does it have? Learn all about FOWLP and our comprehensive tool integration and support for the design and verification of FOWLP products. To read more, click here. » read more

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