CMOS-Embedded STT-MRAM Arrays In 2xnm Nodes For GP-MCU Applications

Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this paper we present an unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS- embedded 40 Mb array. Key features are full a... » read more

Mobile Machine Learning At Arm

Machine learning is playing an increasingly significant role in emerging mobile application domains such as AR/VR, ADAS, etc. Accordingly, hardware architects have designed customized hardware for machine learning algorithms, especially neural networks, to improve compute efficiency. However, machine learning is typically just one processing stage in complex end-to-end applications, which invol... » read more

Meeting The Challenges Of The 2018 National Defense Strategy

In Secretary of Defense James Mattis’ Summary of the 2018 National Defense Strategy: Sharpening the American Military’s Competitive Edge, he provides a critical framework for driving “urgent change at significant scale.” This paper describes the role that Cadence can play in assisting the nation and its partners in achieving that urgency and scale of change called for in the vision and ... » read more

Meeting ISO 26262 Software Standards

Software controls everything from safety critical systems like brakes and power steering, to basic vehicle controls like doors and windows. Yet the average car today may have up to 150,000 bugs, many of which could damage the brand, hurt customer satisfaction and, in the most extreme case, lead to a catastrophic failure. Software development testing is designed to help developers, management an... » read more

Application Of Richardson Extrapolation To The Co-Simulation Of FMUs From Building Simulation

The application of the FMI technology gains ground in building simulation. As far as specialized tools support the FMI simulator coupling becomes an important option to simulate complex building models. Co-simulation needs a master algorithm which controls the communication time steps as well as the signal exchange between FMUs. Often a constant communication step size is applied chosen by the ... » read more

Mentor TLC NAND Softmodel Soft-Bit Error Injection

Designing SSD controllers targeting NAND flash as the storage media requires some heavy lifting when it comes to dealing with the soft-errors that the flash will eventually produce. This paper will look at a method to simplify the design and verification required. We model these soft-bit behaviors with the Veloce emulator in a virtual setup, which reduces the time to market for an SSD. To r... » read more

The Rambus GDDR6 PHY IP Core

The JEDEC-compliant Rambus GDDR6 PHY IP Core is optimized for systems that require low-latency and high-bandwidth GDDR6 memory solutions. Available on leading FinFET process nodes, the PHY interface supports two independent channels, with each supporting 16 bits for a total data width of 32 bits. In addition, the PHY supports speeds up to 16Gbps per pin, providing a maximum bandwidth of up to 6... » read more

TATA Motors Builds HIL Test System For Hybrid Vehicle Simulation Using NI Tools

The Challenge: Developing a scalable, flexible, and universal hardware-in-the-loop (HIL) platform to validate the integration of multiple electronic control units (ECUs) for a parallel hybrid vehicle. The Solution: Using the scalability of the PXI platform and the out-of-the-box functionality of NI VeriStand software to build a test system that could test six interconnected vehicle ECUs toge... » read more

Innovative Integration Solutions For SiP Packages Using Fan-Out Wafer Level eWLB Technology

Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effective... » read more

Bosch Visiontec Case Study

The BOSCH Visiontec team innovates assisted and autonomous driving technology. This team develops state-of-the-art IPs and ICs containing high-performance processors that implement algorithms to recognize images from cameras in automobiles. They were tasked to create several brand-new designs that implemented mathematically-intense algorithms in less than a year. The specifications of these des... » read more

← Older posts