Clock Gating Optimization At RTL

How to efficiently implement clock gating techniques to save power.

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In today’s semiconductor designs, lower power consumption is mandatory for mobile and hand-held applications for longer battery life and for networking or storage devices for low carbon footprint requirements. Clock power can consume as much as 60% to 70% of total chip power and is expected to increase further in the more advanced technology nodes. Hence, reducing clock power is very important. Clock gating is a key power reduction technique used by all designers and is typically implemented by gate-level power synthesis tools.

In this White Paper, we will discuss how SpyGlass Power can help efficiently implement those clock gating techniques. This will be illustrated by design examples to highlight the impact of clock gating on different areas of the design process like metastability with clock domain crossings and testability. This paper also details the do’s and don’ts of clock gating to avoid chip failures and unnecessary power dissipation.

To view this white paper, click here.