Chip research and the chip industry are in no danger of hitting a wall.
By Francky Catthoor
Moore’s Law means that electronic products can constantly be produced more cheaply, faster and more economically. Down to 45nm, this was due mainly to the technology that made it possible to reduce the size of transistors. Now things are becoming more difficult.
But even if we are not able to achieve these gains through the further scaling of transistors as the result of technology alone, Moore’s Law is still not dead yet. Thanks to ever-more ingenious design techniques, we will be able to make up for the difficulties inherent with scaled technology for as long as possible. Imagine, for example, that the default technology in the 7nm node were no longer able to produce gains in energy: this would be partially compensated for with design techniques.
This means that innovations in design will become increasingly important for the further scaling of transistors. Fifteen years ago, I – as a system design specialist – had virtually no connection with technology. That situation has now changed dramatically. Designers and technologists are working increasingly close together to make possible the nodes of the future so that reliable products can be manufactured economically.
That is not only true for logic circuits. You can also use design techniques for memories to improve writability (endurance) by not always using the same cell. Sure, there’s plenty of work being done today in the area of design techniques, but that needs to increase even further. Moore’s Law may well slow down, but it certainly won’t stop.
The 5 nm technology node will still have a large market. These types of scaled technologies are particularly important for density and performance-driven applications, such as servers. Power consumption is not yet playing a major role in this area, although that is slowly changing. But when it comes to embedded systems such as sensors, energy consumption becomes an absolute priority. That’s why design techniques are so essential. The 3 nm node will also be fully explored, probably without a standard MOSFET.
In terms of transistors and circuits this means that new design techniques and models will have to be developed. There will also have to be significant changes on an architectural level. Only on higher design levels will as little as possible be changed. And then we also need to take account of totally new design paradigms: neuromorphic and quantum computing, for example. These also provide an opportunity in subdomains, although no one yet knows whether they will be able to compete with the existing technologies in major markets.
We certainly shouldn’t be looking at the difficulties in scaled technology as a threat, but rather as an opportunity for new developments. Chip research and the chip industry still have a long way to go.
Francky Catthoor is an Imec fellow, and a part- time full professor at the EE department of the K.U.Leuven, where he received the engineering degree and a Ph.D. in electrical engineering. Between 1987 and 2000, he has headed several research domains in the area of high-level and system synthesis techniques and architectural methodologies, including related application and deep submicron technology aspects, and smart photo-voltaic modules, all at Imec.