Design, Test & Repair Methodology For FinFET-Based Memories

A look at new memory test challenges in the finFET ERA and how to deal with them.

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Like any IP block, memories need to be tested. But unlike many other IP blocks, memory test is not as simple as pass/fail. The advent of FinFET-based memories presents new memory test challenges. This white paper covers:

  • The new design complexities, defect coverage and yield challenges presented by FinFET-based memories.
  • How to synthesize test algorithms for detection and diagnosis of FinFET specific memory defects.
  • How incorporating built-in self-test (BIST) infrastructures with high-efficiency test and repair capabilities can help to ensure high yield for FinFET-based memories.

To read more, click here.