The migration to finFET processes requires a serious focus on dynamic power consumption.
Traditionally RTL power analysis has been used to understand the design power consumption so that package and power supply designs can start, and designers can then fix any power regression violations in subsequent design iterations.
However, migration to finFET processes is causing designers to look at RTL power analysis differently at advanced nodes. FinFET processes have largely addressed the power leakage problem that has plagued the design community for many years, but dynamic power consumption has become an acute issue. Combinational clock gating used with logic synthesis is no longer enough to solve this problem. Starting early in the RTL development, designers have to compare and decide on architectures/micro-architectures that significantly reduce dynamic power usage. Because RTL power analysis can help designers assess these design changes, it has taken on a new and important role in the power optimization flow.
Of course, this new role comes with new requirements:
• Out-of-the-box usability, because more designers will want to use it;
• More stringent accuracy specifications, because the analysis affects design decisions;
• Extremely fast, because designers need the ability to evaluate several design choices without impacting schedules.
Early-generation RTL power analysis tools use a model-based architecture. These tools take an average case model built by the user from a typical backend implementation as the reference input, and use it to predict the power number for every design iteration. FinFET power is sensitive to the way the design is implemented in the backend. For example, small changes in clock tree implementation can cause a huge change in the design power. Because a singular model cannot predict power with high accuracy, this model-based architecture does not satisfy all the new requirements.
Later tools use an alternative strategy—a physical prototype-based architecture. RTL power analysis in these tools uses a complete backend implementation with placement and clock tree synthesis. While this approach addresses the accuracy issues with a model-based architecture, building a complete physical prototype takes a long time. That means these tools also fail to meet all the new requirements for power analysis.
Is there a solution that can overcome the difficulties of both model-based and physical prototype-based architectures?
The new smart-synthesis architecture differs from the earlier architectures by breaking the RTL power analysis into two steps:
1. It builds a lighter, gate-level prototype with word-level representation of the design. It also builds an abstract clock tree synthesis (CTS), including multi-bit flop compression and virtual buffering, on this prototype.
2. Using an industry-standard SPEF file from a representative implementation, the prototype is refined with more details. The details include flop and cell selection, actual CTS components, threshold voltage cell distribution, critical operators, and fine-grain wire caps.
Figure 1 illustrates the concept of the smart synthesis architecture.
By breaking the analysis process into an iteration-dependent abstract gate-level prototype generation and an iteration-independent SPEF extraction, smart synthesis architecture overcomes the rigidity of the model-based architecture, and the time-consuming physical prototype-based architecture. It also provides results out-of-the-box, enabling many designers to begin using this solution quickly, without expensive training time. Altogether, smart synthesis architecture satisfies all the requirements of finFET RTL power analysis.
With the migration to finFET requiring RTL power analysis to take an active role in RTL power optimization, new requirements are exposing the limitations of traditional model-based and physical prototype-based architectures. New smart synthesis architecture overcomes these limitations with its unique approach to RTL power analysis. The ability to compare multiple implementation choices quickly and accurately is essential to producing designs that optimize power consumption and usage.
Are you ready to use smart synthesis architecture-based power analysis for your RTL design?