Door Busters In Low Power Optimization

The majority of savings can be realized through SoC-level power exploration.

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The holiday season is upon us, notably a shortened gift buying season at that, which for some only adds to the anxiety felt at this time of year. Many shoppers are out there searching for a door buster deal on that “hot item,” but choices must be made on where to allocate one’s time. Should one stop with the door buster deals or take the time to look further for more practical or traditional gift options?

In retail, the door buster is a sales and marketing strategy used to attract the attention of consumers by offering a discount on a highly sought after item. Once the consumer secures the discounted item, they presumably will look at other items the retailer may offer.
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In EDA, there are several industry offerings or door busters for RTL power optimization grabbing the attention of designers. During this past year there have been many articles, blogs, etc., on automated solutions for RTL modification, vector independent capabilities and improvements in calibration techniques through additional physical means. As power is on the top of everyone’s list, each of these offerings is given fair consideration by design teams. The reality is that we are in the midst of a paradigm shift where these new capabilities require some time to reach the level of maturity whereby design teams gain confidence in their usage.

As illustrated in the diagram below, design teams currently are taking a more pragmatic and methodical approach to power optimization. In a sense, designers are not being overly biased by the attractive door buster. The majority of power savings can be realized through SoC level power exploration, making design decisions at this stage on architecture, power/voltage domain partitioning or targeting IP for further optimization. Next the focus turns to manual power optimization of the most performance-critical blocks in the design. Here, power optimization opportunities are automatically identified, followed by manual modification of the RTL based on tool guidance. Finally, for non-critical blocks in the design, automatic power optimization techniques are utilized. In this case only, automatic modification of the RTL is done, followed by sequential equivalence checking. In summary, power optimization requires a combination of automatic, semi-automatic and manual approaches.

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Whatever your holiday gift strategy this season — pursuit of the door buster, a more traditional approach or patiently waiting for the chaos to settle — you can be assured that like the season’s latest craze, power optimization strategies will continue to evolve and vie for the attention of the design community.