It will be at least two years before EUV is ready, and talk about larger wafers will be stalled until then.
Whether the wafers in question are 200 mm in diameter, or 300 mm, or potentially 450 mm, larger wafer sizes have always been justified by manufacturing economics. If the cost to process a wafer stays the same, but the wafer contains more devices, then the cost per device goes down. For processes that apply to the entire wafer at once — etch, deposition, cleaning, and so forth — the equation has mostly held. Larger process chambers require extra attention to process uniformity, but for the most part have been able to maintain and ultimately increase throughput as the wafer size increases.
And then there’s lithography. Ever since the industry left mask aligners behind in favor of wafer steppers and step-and-scan systems, increasing the number of devices on a wafer has meant increasing the number of exposure fields, even as shrinking critical dimensions have required more precise control of focus and alignment. Exposure tools have thus been expected to move a larger stage more quickly, while increasing positioning accuracy. Given the engineering challenges involved, lithography tools have been amazingly successful in meeting these demands.
Until now. Few people expect to see the same wafer-per-hour throughput for 450-mm lithography that they’ve come to expect at 300 mm. Meanwhile, ongoing delays in the rollout of EUV lithography — currently five nodes behind its original roadmap and counting — have forced manufacturers to consider double-, triple-, and ultimately quadruple-patterning schemes to extend the useful life of 193nm exposures. That’s a problem.
Repeating four exposures across 2.25x as much wafer area adds up to a big throughput hit. Now, multi-patterning schemes are likely to use a combination of self-aligned spacers and additional exposure steps: quadruple patterning won’t necessarily require four exposures per field. Still, in her presentation at the Semicon West IMEC Technology Forum, IMEC’s senior vice president for process technology, An Steegen estimated that if only 193 nm immersion lithography is available the 7-nm node will require 27 masks between the initial formation of FinFET fins and Metal 2. At the 20-nm node, the same portion of the process requires only 13 masks. Reducing net lithography throughput — already a fab bottleneck — substantially erodes the economic argument for the larger wafer size.
IMEC Executive VP Ludo Deferm was fairly blunt in his assessment of the situation. Lithography is a major component of manufacturing cost. For larger wafers to be economically justified, lithography cost needs to come down. For 450-mm wafers to succeed, he said, EUV lithography needs to deliver on its long-promised cost reductions. According to Steegen’s analysis, use of EUV for some exposures could reduce the mask count to 14, of which 6 would use EUV and the rest 193-nm light.
As results presented at this year’s SPIE Advanced Lithography Symposium made clear, however, EUV still has a long way to go to become commercially viable at all, much less cost-competitive with existing technologies. The technology is currently targeting early production in 2016, and Deferm expects it will be 2016 at least before currently stalled 450-mm development even starts to move again.