Executive Insight: Sanjiv Kaul

Calypto’s CEO talks about why power is the top issue for finFET design and how to deal with it.

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Sanjiv Kaul, president and CEO of Calypto, sat down with Semiconductor Engineering to talk about dynamic power concerns in finFETs, where software fits in, and why high-level synthesis is now a competitive requirement at advanced nodes. What follows are excerpts of that conversation.

SE: What’s the biggest problem the semiconductor industry is facing right now?

Kaul: I would put verification very high up on the list. There are about 700,000 servers running RTL simulation. You spend more money on the electricity to run the servers than the software running on them. That’s where the emulation market is growing. But emulation is really for bringing up software. The RTL debug phase remains a major pain point.

SE: And it’s growing not just in terms of RTL debug, but also power in a design, right?

Kaul: Yes, all of that stuff. But even the functional part is a major problem, and there’s no good solution for that right now. The biggest challenge the semiconductor industry will deal with is the dynamic power in finFETs. It’s amazing how much attention it’s getting these days. When I meet with semiconductor companies now, very senior execs show up in those meetings and take copious notes to create action items. Power is something is now sitting at the desk of people right at the top.

SE: Everyone has been predicting this for a while. Why is it suddenly so important?

Kaul: It took the first set of designs to go through and chips to come back. Then it really hit. People went to that technology node and did one set of chips with the existing methodology. It’s when things break that people say, ‘We need to go back and re-do everything we’ve been doing.’

SE: It’s not just at the most advanced nodes, though, right? Even at established nodes power is a top priority.

Kaul: It’s everywhere. The question has been what you need to do about it. A lot of people depend on a power budget, and for them it was running power analysis and making sure they were within the budget. For other people, it’s about differentiation on power. There you’re going to spend a lot of time optimizing power. But if leakage power is 60% to 70% of the power, then you spend a lot of energy focused on what to do about the leakage power. With finFETs, dynamic power has become 70% of the power. You still need to work on the leakage power, but now you need a methodology in place to deal with the dynamic power. Companies like ARM, which have been doing RTL-based design and excelling in low power, have been looking at the microarchitectures. If you talk to ARM, they will tell you, ‘On this chip we were able to reduce power by changing the microarchitectures.’ If you look at all companies for whom power has been important, they’ve been working on RTL and microarchitecture-level power optimization, but the process is a little brute-force. When you get to finFET what happens is some of the existing tools have a hard time dealing with accuracy at the RTL level. That means you really need to come up with a new generation of power analysis technologies.

SE: Does that continue through 10nm, as well?

Kaul: Yes. The physical implementation requires that you do a certain amount of synthesis. The previous generation of power-analysis tools were model-based, and then they gave you 50 knobs to try and match what you were seeing at the gate level. It used to be a process of trial and error where you match gate level on one iteration of a design, and then you would use it as the design evolved. The process breaks down. It was okay when dynamic power was 30% or 40% of the total power. If you misjudged dynamic power by 10% or 15%, your overall power was still reasonably accurate. Now, with dynamic power at 70%, misjudging it by 30% means your calculation is way off. You have to be able to model dynamic power more accurately, and the only way to do that is to understand what the gate-level implementation will look like, and to bring physical information about where are these flops—are they next to each other, are they far apart, are they in the same package—into the power analysis tools.

SE: This is more than just characterization of IP blocks, right?

Kaul: Yes, and building high-level models isn’t enough. We do a quick synthesis—a technology mapping. What typically happens when you’re doing a new design is you’ll do a trial place and route. From that you have enough information to make your RTL power analysis accurate.

SE: Are there enough companies working at the leading edge these days to warrant the R&D investment on your side?

Kaul: Yes, and beyond that I can’t say more.

SE: Which markets are driving this? Is it on the mobility side?

Kaul: Yes. It’s mobility and a little bit of IoT. Now the question becomes how can you get the power optimized. The power analysis will tell you that you have a power problem. Now you need to understand where the power is being wasted and what you can do about it. The problem is that you’re dealing with a power analysis tool that’s 30%, plus or minus. So you make an RTL change and it doesn’t tell you how it’s really going to affect your power. Then you have to go verify whether it’s correct, which means someone has to simulate it. Typically it’s a different team. Then you have to synthesize it. You get it to the gate levels and you run with it. That whole process can take days or weeks.

SE: And it no longer can be done consecutively, right?

Kaul: That’s the problem. We have integrated on a database the ability to make incremental RTL changes. If you want to try something, it only changes that piece of the design. It has a built-in power analysis tool. You can try different things and see the impact in minutes or hours.

SE: So whatever level of detail you need, it’s all there?

Kaul: Yes. That’s what we felt was needed. About two or three years ago we felt this market window was going to open up.

SE: Why?

Kaul: Because of finFETs. People have been talking about finFETs for a while, but the timeline became real a couple years ago. The leading edge got serious about them and began doing designs. We built a whole platform for low power.

SE: Is it starting to roll back into wearables and other IoT markets, as well?

Kaul: Yes. What people do in large volume markets is throw a lot of resources at it. They spend a lot of time doing a lot of analysis. Other companies can’t afford it or don’t have time.

SE: What effect does all of the market consolidation have on this?

Kaul: That consolidation has been going on for more than a decade.

SE: The recent deals do involve bigger companies.

Kaul: Yes, but the dynamic is the same. The cost of equipping foundries is getting too expensive, and the cost of chips is getting too high. So you really need a lot of money to be a player. You cannot get everything right. Everyone does something wrong. So you need sustainability, and that only comes from scale. And then as these technologies get integrated onto one chip, they all need to be under one roof or you need to have control over them.

SE: What impact is the IoT having? Will it drive new business?

Kaul: We hope so. It’s one of the big market drivers. Mobile is one of them. IoT is the other. Anything that drives design will impact us.

SE: What do you think will happen in EDA?

Kaul: In the end there may be three or four companies, because a channel is very expensive to build. You need to have enough product to justify the expense of the channel. As small companies start building differentiation and have products that can be pumped through a bigger channel, then they become attractive to a bigger company.

SE: Still, it’s hard to classify some of the big players as EDA companies because they’re diversifying so much, right?

Kaul: When you have consolidation in your customer base your negotiating position gets weakened. As that continues, it’s like negotiating with Wal-Mart. If you win a deal with Wal-Mart, congratulations, you’ve got the account. But they’re going to leave you with just enough money to keep servicing them. They know exactly what your costs are. Large volume buyers have a lot of negotiating power, and they use it. It’s healthy for EDA players to have other sources of growth.

SE: Doesn’t EDA become a foundation technology for a lot of other ventures?

Kaul: Yes, but because of Moore’s Law you can’t stay still and say you’ve got EDA covered. The ground is shifting underneath you all the time, so you have to keep running fast just to stay up with the latest semiconductor technology.

SE: Is the back end catching up with the front end to the point where you have to worry about things like RC delay and other physical effects?

Kaul: Not at the RTL level. At that level you’re looking mainly at whether you’re able to shut down logic that isn’t being used or whether your microarchitecture is the most efficient from a power perspective. If you run this in a different mode, what does the power profile look like? That’s more at the lower level.

SE: So what happens at the architectural level where the engineering team asks where they can tweak a design?

Kaul: You start off at the architectural level making decisions. Those decisions are made by people. If your design is power-sensitive, then you’ll make decisions at the architectural level that are optimized for power. You also make tradeoffs between performance and cost. Then you go to the micro-architectural level. There may be 5 or 10 ways of addressing the microarchitecture. We’ve created a platform for RTL designers to explore microarchitectures. Then you can synthesize the different microarchitectures for performance, area and power, and make decisions. So if you’re doing multimedia, if you’re not adopting high-level synthesis today you’ll be at a significant competitive disadvantage.

SE: There is movement in two directions. One is at the finFET level. The other is at 28/22nm FD-SOI.

Kaul: If you’re sitting at 28nm and you’re trying to figure out your next implementation, which may be to finFETs, that’s where high-level synthesis comes in. You can re-optimize C for different markets. But C today is mainly for algorithmic blocks, which means it’s well suited for multimedia and advanced communications.

SE: How does software play into this?

Kaul: From a power perspective, software is interesting. Power analysis is only as good as the vector you’re testing, and these vectors are really designed to test functionality. They’re not designed to run the chip in actual usage. If you design a block that goes into a chip, you want to understand what happens when you turn off one thing or run this software on it. The only platform with enough horsepower to run that kind of analysis is an emulator. One of the other things that will have to happen is to bring software onto an emulator to run power analysis.



  • Kev

    “…The only platform with enough horsepower to run that kind of analysis is an emulator…”

    Actually, you are probably better off running Verilog-AMS on GP-GPU if you want power info; emulators are good at 1s & 0s, not real numbers. If you do use an emulator you probably need to dump the 1s & 0s and use secondary tools to work out what the instantaneous power consumption is (e.g. http://www.silvaco.com/products/analog_mixed_signal/inVar/invar.html )