Mentor Graphics’ CEO talks about the growing need for security and what will tip the balance. Plus, changes in EDA, consolidation in the chip industry, and why Moore’s Law is doomed.
Wally Rhines, chairman and CEO of Mentor Graphics, sat down with Semiconductor Engineering to talk about what’s changing across a wide swath of the industry, where the new opportunities will be, when security will become a real opportunity for EDA, and why Moore’s Law will die but progress will continue forever.
SE: Looking back over the past year, what’s changed and where are the possible red flags for Mentor Graphics and the industry as a whole?
Rhines: There have been changes in several dimensions. If I had to point to one product change, it’s the emergence of emulation for anyone doing big digital designs.
SE: Is this the rise of big data in EDA?
Rhines: It’s big data, but it’s also other big digital. We got to the point where you have more than 200 million or 300 million gates and suddenly simulation is not enough. You need emulation. That triggered a doubling of the TAM (total available market), which is a big jump in EDA revenue. The verification task has multiplied by a large factor. On the infrastructure side, it’s been the first year there has been consolidation in the semiconductor industry that is really noticeable. There are some really big acquisitions. There seems to be a lot of liquidity around that is facilitating transactions that don’t happen in more normal time. When a company acquires a company that is as big or bigger than it is, that’s unusual. You don’t see that very often.
SE: Any other changes?
Rhines: Embedded software has become really meaningful for EDA as well as the traditional software industry. Our business has soared and other EDA companies are dipping their toe into different pieces of it.
SE: What’s driving that?
Rhines: In our case it’s system design, particularly automotive, with some aerospace and other industries. The automotive revolution is really in high gear now. Automotive companies are spending a great deal of money to develop the embedded software they need for all of the infotainment, the driver assist, the instrumentation, the networking of the vehicle. It’s taken off because it has to. There are all sorts of requirements. Vehicles will have the most advanced infotainment, but it has to be secure and not hackable into critical systems in the vehicle. So you’re going to have multiple processors. You can’t afford to put a GPU behind every display in the car because you now have a heads up display, the kids’ video in the back, the passenger video in the front, the scanning cameras in the back. Automotive is a big transition that has really taken off in the last year.
SE: How about on the advanced design side?
Rhines: The adoption of finFET and the rapidity with which 14nm and 10nm processes became available is surprising.
SE: Where do you commit your R&D resources going forward? There are some sharp turns ahead—16/14/10/7nm, 28nm, stacked die, vertical markets that didn’t exist before.
Rhines: EDA is a market where it takes a fair amount of R&D just to keep your products up to the latest node of technology, both in terms of complexity and design rules. You have no choice on the existing products. You’re preserving a revenue base. You spend a large amount of R&D on that. But we try to spend as large an amount of R&D as possible attacking new problems for which there is no solution, or new markets that are applications of our existing technology to a new kind of problem. That’s where the revenue growth comes from, and that’s why automotive is such a large area of investment for Mentor. That’s also why we pick a technology like emulation that is not widely used today, but will be widely used, so there will be additional TAM growth there as compared to traditional EDA—PCB design, RTL simulation, place and route. All of these are TAMs that, if they grow, they grow very slowly. Things that are really driving up EDA’s TAM are solutions to new problems and applications of EDA to non-traditional problems. In the last 15 years, most of the growth of the EDA TAM has been IP, design for manufacturing, including optical proximity correction, emulation, power analysis and embedded software.
SE: You spoke at Mentor’s User2User group about the growing need for security. Where does that fit in?
Rhines: That’s a hot topic today, as well. You can always get someone to listen to you if you have something to say about security. Most of the money being spent today is being spent at the higher levels, such as application software and maybe a little down at the operating system level. There is very little being spent on security for silicon. That potentially is one of the most threatening, and also one of the most difficult to control. So it’s my expectation that over time that will be a large part of what EDA companies do—build tools that design in security into the products being sold.
SE: Going back several years ago, you said security would be part of the verification effort. What’s your thinking on that today?
Rhines: Design will be the place where people spend the most time worrying about silicon chip security. In the past it has been process. The government has run secure foundries out of fear that people could get into the foundries and sabotage the process, or they could get access to the database and derive the algorithms in the chips from the physical layout. Today, it’s obvious that a much bigger threat are the things that can get into a design, either from IP that is purchased or that you get off the Internet, or IP that is created even in your own organization that contains things that will provide vulnerabilities in the chips you develop.
SE: And not all of them malicious, right?
Rhines: It’s both. You need to be proactive. You need to be designing in things to make sure the likelihood of something both can exist and can be activated in the chip. So it’s active protection against intruders that hack through as well as verification to make sure the IP you have does not have unwanted things in it.
SE: What’s your play here?
Rhines: All the EDA companies are developing tools that will help you design security into your chips. There are a whole variety of proposals for things that can be done. The award for best paper at DAC this year was awarded for physically unclonable functions. Those are all things we know how to do, but the average chip company doesn’t want to go to the additional cost and complexity unless then need to.
SE: That increases the price of the chip, the IP, and the integration process, right?
Rhines: Yes, and there are vaults associated with keywords. And volume manufacturing has somewhat of an impediment if each chip has its own unique encryption key. It adds cost in a lot of different ways.
SE: When do we start seeing these tools rolling out of EDA companies?
Rhines: You’re already seeing some startups offering some things. Over the next year you’ll see it out of the EDA companies, as well. But I also think it doesn’t become big until there’s a crisis.
SE: You mean like the IRS getting hacked?
Rhines: A little different, like someone getting physically hurt or someone breaks into a vault and erases your bank balance, or there is some kind of security threat from a foreign government that gets into a piece of military equipment. When a crisis occurs, the normal reaction is for the customers of the chip companies to come to them and ask them to certify that the chips they’re selling contain no Trojans or unwanted viruses that might be a problem. The chip companies will go to their lawyers and ask, ‘Is it okay if we sign this guarantee?’ The lawyers will say no. That’s when the fun starts.
SE: But are we prepared for when that day comes, or are we still too far out in front of the market? And what’s the scenario for getting there?
Rhines: First of all, people have to be willing to pay for it, and willing to go through the trouble to install it. There are people who are willing. They tend to be in the military or high-security operations. But the average consumer of chips today does not want to bear the cost.
SE: What does that do to the fundamentals of chip design, because it adds extra circuits, extra power drain with always on, always patrolling?
Rhines: This is what the semiconductor industry and EDA are all about—doing more for less. You’re adding circuitry, complexity, an enormous amount of verification you didn’t have to do before, and the design or verification engineer who was struggling to make sure the chip did what it was supposed to do, now has the task of verifying it’s not doing anything it’s not supposed to do. That’s an infinite space of possibilities. It’s quite difficult to do it with certainty. But like “The Club” on the steering wheel of your car, it makes your car more difficult to steal than other people’s cars. Maybe they’ll go hack into other people’s chips.
SE: So rising security risks are good for EDA?
Rhines: EDA only grows when something breaks. That’s one thing that can easily break in the near future.
SE: Can you extend that opportunity into software, as well?
Rhines: Absolutely. A big key to the embedded software that we provide to automotive companies is the embedded layer that exists with it—the firewalls, the hypervisor, the multiple operating systems in an automobile. They have to run through a hypervisor and be protected, so the vehicle infotainment can incorporate your iPhone and other stuff you bring into the vehicle without penetrating through to mission-critical functions in the car.
SE: Hypervisors traditionally have not been the most secure, though. What’s changing there?
Rhines: Our hypervisor and our software have to be certified to all sorts of standards. ISO 26262 will be added to that, but today it’s the aerospace standards and a list of about four or five of them. Those all have requirements that at least have some element of what you’re talking about.
SE: One other big story for this year is Moore’s Law and the rising pain levels of moving to the next node.
Rhines: Moore’s Law is a special case in the learning curve. It says we will reduce the cost per gate or transistor as we increase the total volume of transistors we produce. And that will continue to forever. Moore’s Law will not continue forever. It says that if you can shrink feature sizes and wafer diameters fast enough, then you can stay on the learning curve just through that mechanism. Sooner or later, you’ll have to do other things, because shrinking feature sizes will become too expensive to keep you on the learning curve. You need to use other methods in addition to shrinking feature sizes.
SE: At some point in the next node or two we’re going to start encountering quantum effects, where electrons don’t move through wires as quickly or regularly as in the past. What effect does that have?
Rhines: That comes along with electromigration, electromagnetic interference, thermal effects and so on. As we continue down the evolution of circuits these problems keep popping up. They’re great opportunities because then we develop tools to analyze the problem and fix the problem. The kinds of things you’re talking about—the statistical distribution of electrons or the cross-sections of metal—those kinds of limitations do have solutions. And those kinds of solutions are based on playing with statistics. You can have redundancy, repairability, different device structures. I once made a mistake in a speech of saying there is a limit to memory cell electron storage as you got down to 1 electron, and someone sent me a paper saying you do not need 1 electron per bit in a storage cell in order to have one. I’m more careful about making statements like that now.