Executive Insight: Wally Rhines (March 2018)

Wally Rhines, president and CEO of Mentor, a Siemens Business, sat down with Semiconductor Engineering to discuss a wide range of industry and technology changes and how that will play out over the next few years. What follows are excerpts of that conversation.

SE: What will happen in the end markets?

Rhines: The end markets are perhaps more exciting from a design perspective right now than they have been in recent years. Everyone is intrigued with the electronic design opportunities that have been emerging in the automotive industry. The technology development race in automotive has re-awakened and accelerated development that has spilled over into other industries. The value consumers attribute to electronics and software of some vehicles is said to be reaching nearly 50% of the purchase price. This results in significant attention by the OEMs and suppliers into all things related to electronic and software design. Industrial electronics is another exciting area with the adoption of Industrial Internet of Things (IIoT). Smart factories and supply chains are rapidly becoming a basic requirement to remain competitive. Intelligence is driving yield, cost and scheduling, allowing factory managers to make intelligent decisions at any moment while keeping inventory levels optimized.

SE: How about in other markets?

Rhines: IoT technology is finding meaningful applications in the home. We all have stories of connected devices that don’t solve a real world problem. However, those missteps have been giving way to real solutions that are helping to drive the consumer industry. Just as meaningful to both consumer electronics and industrial electronics are the developments in vision. Cameras are an important input to many devices, as well as the assembly line. This Christmas season many 4K TVs were exchanged as gifts, a result of years of development with many other vision-related devices on their way. Visual information has helped drive technology change in communications and computer industries with its demand for bandwidth, storage, performance and network capacity. It is an exciting time to be a technologist in virtually any industry.

Photo credit: Paul Cohen/ESD Alliance

SE: How about within EDA. Is anyone going to make a run for Cadence or Synopsys?

Rhines: I don’t know. For Mentor, the benefit of joining Siemens PLM has been significant, but this was one of the few acquisitions that targeted increased investment in the acquiree rather than cost reduction. As a result, Mentor has been able to increase IC Design R&D, make key acquisitions like Solido and take advantage of Siemens’ customer relationships to accelerate the adoption of EDA by systems companies.

SE: Why is Samsung allotting so much for capital expenditure? And will the rest of the industry respond?

Rhines Samsung’s historic investments underline a belief in their own future as a technology and market leader in their semiconductor and display businesses. Samsung is just exercising their market advantage versus all of its rivals with their ability to invest at this moment in time. Any businessperson knows that a pretty solid case has to be behind that level of investment, so they clearly have a plan. And this level of investment will force market change. Rivals will have to respond, or perhaps be satisfied with the potential of becoming a smaller part of the market going forward. The response may be strategic rather than in just increased spending. Not many can spend to those levels. Some of their rivals will choose to specialize. Others might merge or consolidate. Merger options could include both vertical and horizontal alternatives. The answer to the prior question might even be impacted. There is a broad range of market responses that might occur. There are some very smart executives at Samsung’s rival companies reviewing their options right now. Passive acceptance by rivals is probably not a good alternative.

SE: Will Portable Stimulus see light of day in 2018?

Rhines: The short answer is yes. Accellera released an “Early Adopter” spec for public review at DAC in June, 2017 and is currently working toward a 1.0 release in 2018. The plan of record is to have a “1.0 Preview” version available at DVCon (U.S.) for another 30-day public review period. Then they will do one more cleanup pass and submit it to the Accellera board for approval in May. The expectation is that the Board will approve the Portable Stimulus Standard 1.0 version in June, 2018, prior to DAC. Mentor will have Questa inFact fully updated by then to fully support the new standard when it comes out. We expect the Portable Stimulus standard to be the next advancement in abstraction and productivity for SoC verification. It is important to point out that we do not expected it to replace UVM, but rather be complementary to UVM to improve coverage closure, verification efficiency, and effectiveness at the block level. We believe that the ability to re-use the verification intent expressed in PSS – from a block-level UVM environment to a software-driven, embedded-processor SoC environment and on multiple platforms (simulation, emulation, FPGA prototyping) – will provide a quantum leap in productivity. Because Portable Stimulus specifications are declarative, tools can fully analyze the verification-intent description at the system level and generate multiple correct-by-construction implementations of use case tests on multiple platforms, from a single specification, without requiring verification teams to rewrite the tests in UVM for the blocks and C for the system.

SE: Can we expect to see continued advances in IoT, machine learning, medical and what kinds of devices or services may get announced?

Rhines: The way we see it is that IoT, AI, machine learning and autonomous driving are all interconnected. The Internet of Things continues to capture more data. Machine learning and AI help us sort, filter and use this data to better understand and predict things faster than humans can. For example, autonomous driving will leverage AI to identify threats on the road not visible to the human eye and react to avoid those threats faster than humans can. These vehicles will also become things/nodes in the IoT, transmitting an enormous amount of data to OEMs for predictive maintenance as well as to infrastructure so drivers can determine the fastest route to reach their destination. What’s more, the upcoming shift to 5G connectivity will enable a more sophisticated generation of IoT, with more advanced AI “things” to communicate larger amounts of data even faster. We believe with 5G we’ll start to see not only a quickening of advancements in technologies for autonomous vehicles, but also for smart factories, smart hospitals, smart cities, communications infrastructure, and business intelligence, so companies can leverage real data on usage and preference to tailor products to customer needs – perhaps before customers even realize they need them).

SE: What does this mean for the semiconductor industry?

Rhines: Appropriately, we believe there will be a surge in the number of companies producing SoCs with AI cores/IP for the things/nodes in the IoT. There also will be a surge in the number of new AI-processors, which likely will include some form of acceleration, for data centers and cloud infrastructure. We’ll also see an IC build out supporting wireless communications infrastructure for 5G, and then a build out for a new generation of IoT devices that can take full advantage of the massive bandwidth 5G promises. The wired networks also will see a boost from more ICs using silicon-photonic processes that bring speed-of-light fiber optics directly to ICs. Of course, all this will require more advanced tools and methodologies for developing IC architectures, functional verification, physical design and verification, yield and advanced testing. We’ll also begin to see greater emphasis on design for reliability and greater incorporation of high reliability design techniques even perhaps self-correcting architectures for the devices in the IoT and infrastructure. And these ICs will need to be tested in the context of all system levels, not just the SoC system, PCB or ECU, but the entire automobile or fleet of automobiles in a network. It’s wonderful to live in an era where so much change is being driven by technology. Needless to say, this era represents a great opportunity for growth for the EDA, semiconductor and electronic system industries.

SE: What will happen on the semiconductor manufacturing side?

Rhines: 2018 will mark the year where the leading foundries started to ramp 7nm technology (or equivalent). Most 7nm initially will rely on the established lithography technologies, specifically 193nm immersion and multi-patterning – both self-aligned methods (SADP/SAQP) and regular DP/TP/QP. It is expected that foundries will start to introduce EUV perhaps later in the 7nm rollout, or even when they move to a “half node.” Foundries currently are managing design rules to address both non-EUV and EUV approaches to patterning. The Calibre design and manufacturing tool suite supports all required multi-patterning approaches, and it includes specific considerations for multi-patterning interactions when applying process corrections to design data. In addition, we’ve enhanced the Calibre tools to address the growing 2D and 3D interactions in IC designs at the 7nm node. It’s also worth noting that that in 2017 we saw significant new announcements of fab capacity in China. We expect that will progress in 2018.

SE: EUV use is beginning, and there are plenty of new materials and new memories showing up in the market.

Rhines: The industry is considering new resist materials to address the strong stochastic effects that are currently observed with the EUV exposures. Cobalt is being introduced for metallization in advanced nodes. We have been working closely with all the foundries.

SE: Will we see any significant changes in design practices or new development tools?

Rhines: With every cycle of , each new technology node introduces new challenges in terms of capacity and complexity throughout the IC design flow. The latest process nodes, plus the functionality requirements for macro market trends (increased autonomous driving, AI, vision, IoT, 5G, among others) introduce additional complexities and reliability requirements, which impact how ICs are designed and the tools and methods required to design them efficiently. At the SoC architectural level, there’s a greater need for companies to implement the optimal architecture with the right balance of functionality, power and performance. Design teams (especially those starting with algorithmic approaches for developing AI and pattern recognition into their designs) are finding that starting architectural discovery with C-level synthesis allows them to quickly develop multiple architectural schemes and converge and implement the best one for their given application. This reduces RTL development time and license requirements and speeds time to market. We are seeing exponential growth in this business, and expect that will continue as more companies realize that starting at the RT level is starting a growing distance behind the competition.

SE: How about verification?

Rhines: Over the past 10 years we’ve seen an explosion of new verification requirements. For example, beyond the requirements to verify the traditional functional domain issues, we have added clock domains, power domains, mixed-signal domains, security domains, safety, software, and then obviously overall performance requirements. This is driving the need for multiple focused solutions and technology optimized for specific verification concerns. Examples of these focused solutions include formal apps used to verify security features within a design, and power apps used to provide complete RTL power exploration and accurate gate-level power analysis within emulation. We also are seeing a need for greater convergence across multiple verification engines (simulation, emulation, and FPGA prototyping, for example). This is necessary to improve productivity across the design teams from IC design to software development. And our industry is addressing these concerns through the development of the new Accellera Portable Stimulus Standard (PSS), which will help facilitate this convergence and foster the introduction of new verification solutions and technology.

SE: Where does analog/mixed signal fit into this?

Rhines: We believe 2018 will see significant growth in new analog and mixed-signal ICs and IP for automotive, communications, data-center computing, networking, mobile, and IoT applications. The challenges in verifying these high-performance and low-power analog and mixed-signal circuits will continue to put stringent requirements in the verification flow and verification tools. The circuit verification flow will need to deliver the foundry-certified circuit simulation accuracy with improved performance and capacity. Simulation will need to include the effects of device noise, post-layout parasitics and process variability across multiple environmental and operational conditions. Mentor continues to invest in technology to address these challenges as evidenced by the recent acquisition of Solido for variation-aware design. On the AMS and full custom design front, we are seeing a rapid increase in the number of IT companies, such as Google, Alibaba, Facebook and Microsoft, developing their own ICs for their own IoT products. From those they can derive customer data, which they can then leverage for further business. They are looking for modern integrated/all-in-one custom design solutions to develop the ICs for these IoT products. And across the IC EDA tool portfolio, we are now seeing multiple opportunities to leverage data analytics and machine learning to solve a variety of engineering problems-ranging from significantly reducing standard cell, memory, and I/O characterization time, to providing deep functional and performance insight through system-level analysis.

SE: What about industry consolidation?

Rhines: Over the last several years, the semiconductor industry has experienced a wave of consolidations. The number of yearly mergers and acquisitions with a combined value over $50 million doubled from 2013 to 2016-jumping from 16 to 34. But this year, mergers dropped dramatically to 15, even with the recent announcement of Marvell purchasing Cavium. However, the value of announced mergers reached an all-time high of $156 billion, if you include Broadcom’s offer to acquire Qualcomm. That’s nearly seven times 2011’s $23 billion in M&A-which at the time was an all-time high for the semiconductor market. So why this surge in consolidations? The most widely accepted reason is that the 60-plus-year-old industry is maturing and following the well-trodden path of other established industries such as steel and automotive. But the data does not support that hypothesis. The combined market share of the 50 largest semiconductor companies is still less than it was 10 years ago. And the combined market share of the 10 largest semiconductor companies is only 10 points higher than the average of the last 40 years.

SE: So what’s really going on?

Rhines: Another possibility, which I believe to be more likely, is that we are in between major waves of growth that are typical of the semiconductor industry. Wireless handsets propelled the most recent wave of growth, and we are waiting for something new, like the Internet of Things, to generate a new wave. Historically, new semiconductor growth is ushered in by new applications that become possible when the cost per function, or some other new capability, makes the new application possible. In recent years, the cost per transistor for semiconductors has decreased more than 30% per year, just as it has, on average, for most of the last 60 years. It’s likely that continuation of this trend will, in fact, enable future waves of new semiconductor applications. In the meantime, the continued low cost of borrowing and other factors such as market specialization will provide fuel for some level of increased industry consolidation. But that consolidation is likely to show up as increased dominance by specific companies in focused application segments.