Experts At The Table: The Business Of IP

By Ed Sperling
Low-Power/High-Performance Engineering sat down to discuss IP supply chain issues with Jim Hogan, an independent VC; Jack Brown, senior vice president at Sonics; Mike Gianfagna, vice president of marketing at Atrenta; Paul Hollingworth, vice president of strategic accounts at eSilicon, and Warren Savage, CEO of IPextreme. What follows are excerpts of that conversation.

LPHP: Do the originators of the IP test with a different set of tools than what the tools vendors test it with?
Gianfagna: In some cases it’s different tools, in some cases it’s the same tools with a different methodology. If we can all agree on a consistent and repeatable way to design and deliver IP, that helps.
Browne: You have to highlight the areas you want to look at. We’re delivering Verilog IP with a million lines of code. There’s Perl, C, Verilog, SystemC. We have a hard time finding the experts to create this stuff, and an even harder time finding someone to go in and look at the rules violations. It’s far better if you can tell people these things are clearly wrong and you need to check these things. We use tactical cells that allow people to plug in their favorite memory retention. If you want to turn something off and turn it back on and remember exactly where it was—we don’t define those cells. You know you’re going to get warnings if you run it through Spyglass. But it’s one more value to uniquely tune a solution and we’ve told the customer where they need to watch out.
Hogan: Apple has scenario managers that they test their power against. They have 57,000 situations they simulate against to build a distribution of what power consumption is. The CPU guy across town has 20,000 of these. They keep throwing these at the device until their comfortable with the power escapes. If you look at an IP block that’s going on an SoC and you just focus on power, you have to run 57,000 iterations on power management. The problem is getting complex, but it’s not because the SoC is growing and the underlying semiconductor process has gotten more difficult. It’s the software that’s killing us. Whoever fixes that will make a lot of money.

LPHP: This is still the only industry where you can buy something and it will never be guaranteed to work. Will that ever change?
Browne: It could work if you were willing to run at 10MHz. But it’s also the only industry where the supply chain is as big as this. We’re frustrated because we can’t choose from 300 IP providers and make sure everything perfectly plugs together. The flip side of this is that you have 300 IP providers because evidently someone had a problem after there were only 299 of them.
Gianfagna: But is there an opportunity for indemnification?
Savage: It doesn’t work because you may have a manufacturing defect.
Browne: You can’t indemnify $1 billion worth of profits at Apple. If you want my unique value, you should make the indemnification so it’s the right size for my little company as your supplier. We should be partners.
Gianfagna: Is this a business opportunity for the insurance industry. If people design IP in an ad hoc manner, no one will guarantee anything. But if we can come up with a methodology and process that can be shown to dramatically reduce the probability of errors, that can become an opportunity.
Savage: We’ve had that discussion in a number of the GSA working groups. It all comes down to who’s going to pay the premium. Is it just going to be another cost burden for the IP provider?
Hogan: I’m not licensed to practice law in any state, but I have bought indemnity packages for products. There’s no way you can indemnify $25 billion worth of phones. But you can indemnify companies for their development costs. So you can have reasonable indemnification. But will software ever work flawlessly? No.

LPHP: But if your phone is working two hours instead of four hours, how do you really define “working correctly??
Hogan: You can’t, and there are so many benefits to the new stuff that you can’t go backward. But what’s the motivation to move to the next phone? Do you want better display or 4G LTE?

LPHP: What happens when we start stacking die? IP may be an entire die that’s a known good die, but in a stack it doesn’t work.
Hollingworth: We’re just in the early days of that now, doing real projects. We’re working on 2.5D, which is not actually stacking vertically. That will happen, but it’s out there and there are still some problems to solve, such as long-term reliability of silicon where you have through-silicon vias running through active circuitry. The big challenge there is heat. How do you get something that’s dissipating a watt sandwiched between two other very thin layers. With 2.5D that’s no problem. So just because you have a tile that’s proven to work doesn’t mean it’s going to work next to everything else. It’s not that different from an IP block, though. Just as Sonics stitches together IP blocks, we need a methodology that stitches together these individual tiles. You’ve got issues like electromigration, heat management and voltages that might be old 0.13 micron stuff. That has to evolve over time. The first step is to solve the clear issues we see today, and the biggest one there is memory bandwidth. The DDR4 standard is great because DRAM will run twice as fast, but for decades we’ve had a quadratic increase of the capacity of the chip and DRAM wasn’t keeping up. If you look at the big network processors, they have as many as 15 or 20 DRAMs just to handle the packet-buffering bandwidth. Terabit rates are required. That’s an obvious reason for putting a processor next to a memory stack, and that’s a fairly well constrained problem. We’ll add SerDes and PHY and other things, but it will take a while.
Hogan: We talk about all the problems in a stacked die. Here are my reasons for doing it: If you pull the analog and RF off onto a different chip and a different process and you have discrete DRAM and have your SoC controller sitting on an interposer, then you can manage the voltages and yields differently. Is that cheaper than doing an SoC from scratch?
Browne: We don’t deal with stacked thermal hotspots today.
Hogan: But there’s nothing new here. We used to call those hybrids. Interposers are this generation’s version of the same thing. When you can’t figure out how to do it in silicon and integrate it economically or reliably, then you come up with an interposer. There are all kinds of problems. There are reliability issues, mechanical issues, modeling problems because every TSV is an antenna, but this is only going to be a problem for a while.
Browne: Statistically we’ll get this right eventually.
Savage: It also means that IP can live longer because it can stay in older nodes longer. Foundries producing 0.18 and 0.13 can continue to make it. IP already has an extremely long life. That adds more revenue life to IP companies without investing in the latest 28nm or 20nm. It’s good for IP companies. If you look at the lithography roadmap, do you really want to stay on that?