Fab Tool Biz Faces Challenges In 2017

Outlook strong for some sectors, tepid for others. Consolidation, rising costs of development could take a toll.

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After experiencing a gradual recovery and positive growth in 2016, the semiconductor equipment industry sees a mixed picture as well as some uncertainty in 2017.

In the near term, though, business is robust. Several chipmakers started to place a sizeable number of fab tool orders in the latter part of 2016, particularly in three areas—3D NAND, logic and foundry.

Now, after buying the initial round of equipment, chipmakers are expected to remain relatively cautious about adding any new fab capacity, at least in the near term.

Chipmakers could place additional fab tool orders if or when demand picks up in 2017. But based on the current demand picture, tool orders could gradually level out and then wane throughout 2017, leading to flat growth in terms of capital spending for the year, according to one analyst.

“Near term, semiconductor equipment demand is strong, led by heavy (calendar) Q4 spending by Samsung for 3D NAND and 10nm installations at TSMC and Intel,” said Weston Twigg, an analyst with Pacific Crest Securities, “(but) semiconductor capex growth may decelerate in 2017.”

In total, worldwide semiconductor capital spending is projected to reach $63.9 billion in 2017, up a mere 1% over 2016, according to Twigg. In comparison, semiconductor capital spending is expected to grow by 9% in 2016, he said.

For now, Pacific Crest sees single-digit capital spending growth in two of the four major fab tool sectors in 2017—foundry and flash. Two other sectors, DRAM and logic, are projected to be slightly down.

On the bright side, the 200mm equipment market looks robust. These projections, of course, could all change, depending on market conditions as well as economic and political factors.

On top of that, the equipment industry is seeing another trend, namely that the days of the mega-mergers are over. In 2015, for example, Applied Materials’ proposed acquisition of Tokyo Electron Ltd. was scrapped due to regulatory issues and customer pushback. And in 2016, Lam Research’s move to buy KLA-Tencor was terminated for similar reasons.

Both regulators and chipmakers were reluctant to bless the mega-mergers for three basic reasons. First, the mega-mergers ostensibly create monopolies in some tool segments. Second, consolidation could slow, if not stunt, innovation. Third, it reduces chipmakers’ buying power.

The equipment sector is still seeing some acquisition activity, but it’s on a much smaller scale. For example, ASML recently acquired Hermes Microvision, an e-beam inspection specialist.

To be sure, the semiconductor equipment and materials industry is a large but fragmented market. To get a handle on what’s ahead in 2017, Semiconductor Engineering has taken a look at the business dynamics as well as the various segments, such as silicon wafers, photomasks and fab equipment.

Mixed numbers
2017 looks like a mixed bag. In total, the IC market is expected to reach $306.8 billion in 2017, up 6.1% over 2016, according to VLSI Research. In 2016, the IC market is expected to grow a mere 1.7%, according to VLSI Research.

The overall semiconductor equipment market is expected to reach $58 billion in 2017, up 7.8% over 2016, according to the firm. In 2016, the equipment market will grow 10%.

In another forecast, Applied Materials projects that the overall wafer fab equipment (WFE) market will range from $33.5 billion to $34 billion in 2016, up 5% over 2015. For 2017, WFE is expected to increase by $1 billion over 2016, according to Applied.

“In 2017, WFE looks to be even higher, with spending growth for memory technologies and investment for logic and foundry remaining at robust levels,” said Arthur Sherman, vice president of marketing and business development at Applied Materials. “Market segments we think will fuel industry growth for years to come are leading-edge foundry and logic, 3D NAND and patterning.”

Still, the market is changing for fab tool vendors. Over the years, the base of leading-edge chipmakers has undergone a wave of consolidation. Fewer IC vendors can afford to buy leading-edge tools. In total, five chipmakers represent about 75% of worldwide capital spending today, according to data from Lam Research.

With fewer leading-edge players, though, the equipment market is more predictable and less volatile, as compared to the wild boom-to-bust cycles in the past.

The demand drivers for semiconductors are also changing. The PC, once the big driver for chips, is declining. The smartphone market is still the biggest driver for silicon, but the business is seeing flat growth.

“The world of tech is no longer defined around one dominate electronics product like the PC,” said Martin Anstice, president and chief executive of Lam Research, at a recent event. “There are a multitude of consumer and enterprise applications drivers.”

Among those drivers include automotive, IoT and wireless. “If you look at the big picture, there are three basic vectors people are working on,” said James Truchard, president and chief executive of National Instruments. “One is the data rates. We all want to get our videos faster. We don’t want our neighbors interfering with our videos. (In addition), things like autonomous vehicles will require much faster response times. And then, of course, we talk about billions of Internet of Things at really low power that can stay online for years.”

The building blocks—wafers and masks
One way to get a pulse on the IC market is to look at the demand picture for two key building blocks in the sector—silicon wafers and photomasks.

Silicon wafer makers produce and sell raw silicon wafers to chipmakers, which in turn process them into chips. In 2017, silicon wafer shipments are projected to reach 10,642 million square inches, up 2% over 2016, according to SEMI.

The photomask market also is seeing modest growth. In 2017, photomask sales are expected to reach $3.4 billion, up 3% over 2016, according to SEMI.

That doesn’t tell the entire story about the photomask market, however. In fact, this industry will likely see some new and major innovations in 2017.

screen-shot-2016-12-13-at-3-52-00-pm
Fig. 1: Number of steps increases for multi-patterning. Source: Lam Research.

The first innovation is the advent of multi-beam mask writers. Today, mask makers use single-beam e-beam tools to write patterns on a mask. But with these systems, the write times are becoming too long for the most complex masks.

The newfangled multi-beam mask writers promise to boost the write times for complex masks. In 2016, IMS Nanofabrication announced the world’s first multi-beam mask writer. NuFlare is working on a similar system.

“Several mask shops are doing early testing of the multi-beam machines in 2016,” said Aki Fujimura, chief executive of D2S. “2017 will definitely see some test applications and perhaps even production applications for multi-beam. This, in turn, will lead to enabling curvilinear shapes and smaller features requiring slower resists on masks to become available for wafer lithography.”

In addition, the industry is preparing for the possible insertion of extreme ultraviolet (EUV) lithography at 7nm and/or 5nm. Using a 13.5nm wavelength, EUV promises to simplify the complex patterning flow.

EUV is making progress, but it is still not in production. There are still issues with the source, resists and masks. “EUV masks will be a much higher priority in 2017,” Fujimura said. “As the industry readies its infrastructure for EUV production in the 2020 timeframe, the mask infrastructure needs to become ready in the 2018 timeframe.”

WFE—foundry/logic
On the fab side, it’s also a mixed picture. After a down year in 2015, fab equipment makers experienced a rebound in both logic and foundry in 2016.

In 2017, though, the logic and foundry markets are expected to be relatively flat. For logic, semiconductor capital spending is projected to reach $12.8 billion in 2017, down 1% over 2016, according to Pacific Crest. In 2016, capital spending for logic is expected to grow 11%, according to the firm.

For foundry, capital spending is expected to hit $20 billion in 2017, up 2% over 2016, according to Pacific Crest. This compares to projected growth of 5% in 2016.

In 2017, Intel, Samsung and TSMC will make the transition from 16nm/14nm finFETs to 10nm finFETs. Both Intel and Samsung believe that 10nm will be a robust node.

In contrast, TSMC says 10nm will be a short node and is putting more emphasis on 7nm. GlobalFoundries is skipping 10nm and moving directly to 7nm.

Initially, Intel will ramp up 10nm in Fab 28 in Kiryat Gat, Israel. Over time, Intel also plans to produce 10nm in Fab 32 in Chandler, Ariz., sources said.

Samsung is ramping up 10nm in a fab in Korea. And for both 10nm and 7nm, TSMC will use Fab 12 in Hsinchu, Taiwan, as well as Fab 15 in Taichung.

In total, the worldwide capacity for both 10nm and 7nm is projected to be somewhere between 110,000 to 130,000 wafer starts per month in 2017, according to analysts. “Most of the investment that we’ve seen so far in terms of production investment has been for 10nm,” said Rick Wallace, president and chief executive of KLA-Tencor, in a recent presentation. “We have seen investment for the development in 7nm and even some looking forward to 5nm.”

The jury is still out if 10nm and 7nm will become successful nodes. Needless to say, fab tool vendors hope that both nodes are robust. If so, vendors could see sizable growth in several equipment sectors.

For many fab tool vendors, patterning is one of the bigger growth sectors. From Applied Materials’ standpoint, the overall patterning market is expected to grow from $2.2 billion in 2016 to roughly $3 billion in 2019. This involves both DRAM and logic.

Patterning involves printing tiny features on a wafer. For this, chipmakers use today’s 193nm immersion scanners, plus various reticle enhancement technologies.

For logic, these solutions ran into resolution problems starting at 22nm/20nm. So to extend IC scaling, chipmakers moved to multiple patterning. Basically, in multiple pattering, a mask is split into two or more masks. Then, each mask is processed and printed separately.

In the fab, lithography tools are still used in multi-patterning. But each new node also requires more deposition and etch steps, which help scale or reduce the pitch of a device.

Multiple patterning has its pluses and minuses. On one hand, some equipment vendors are able to sell more deposition and etch tools, thereby boosting their bottom lines. But it also adds cost and complexity for chipmakers and their processes. For example, there are two times as many deposition, etch and clean passes or steps at 7nm, compared to 16nm/14nm, according to a presentation from Lam. At 5nm, there are 2.2 times as many steps over 16nm/14nm.

As the number of steps increases at each node, chipmakers face a number of challenges. Cost and variability are just the tip of the iceberg.

That’s why the industry wants EUV. If it works, EUV could reduce the complexity and the number of steps. At the same time, EUV could also take a bite out of the overall multiple patterning pie—at the expense of the deposition and etch tool makers.

EUV won’t dominate the entire multi-patterning landscape, however. “Our model is consistent with others and assumes that EUV will primarily be used for cuts and vias in foundry and logic applications,” said Gary Dickerson, president and chief executive from Applied Materials, in a recent presentation. “That’s about 20% of the total patterning market. For the other 80%, we see customers expanding multi-patterning solutions and this significantly grows our addressable market.”

Besides patterning, chipmakers will require other fab technologies at advanced nodes. Atomic-level processing techniques, such as atomic layer etch, is a key enabler. In addition, the interconnects—those tiny wiring schemes in chips—will require new tool types and materials. And it will require more advanced inspection and metrology tools.

Memory shifts
Meanwhile, memory is like a tale of two cities—NAND is hot, while DRAM is down. Capital spending for the DRAM sector is projected to reach $10.3 billion in 2017, down 1% over 2016, according to Pacific Crest Securities.

For DRAM makers, though, the challenges are increasing. In fact, DRAM vendors are migrating from the 2xnm to 1xnm nodes. Patterning and scaling the capacitor are just a few of the challenges.

“While demand for DRAM will be up slightly next year, we don’t see high levels of DRAM spending,” Applied’s Sherman said. “That may change in 2018 for DRAM, along with some of the alternative new emerging memories we’re starting to see.”

In comparison, capital spending for the overall flash sector is projected to reach $18.3 billion in 2017, up 3% over 2016, according to Pacific Crest Securities.

NAND flash makers are expanding their capacity. Samsung, for example, is building its new mega-fab in Pyongtaek, Korea, which will move into production in late 2017. The fab can be used for NAND, DRAM or logic, although the early tool orders are being placed for NAND, according to Pacific Crest.

Today’s planar NAND is nearing its physical limit at the 1xnm node, thereby requiring a new technology—3D NAND. Unlike 2D NAND, which is a planar structure, 3D NAND resembles a vertical skyscraper. A 3D NAND device consists of multiple levels or layers, which are stacked and then connected using tiny vertical channels.

In planar NAND, the fabrication process is dependent on lithography. In 3D NAND, though, the challenges shift from lithography to deposition and etch.

3D NAND is more difficult to make than previously thought, however. Samsung has solved the problems and is shipping 3D NAND. Other vendors are still wrestling with the technology.

In 2017, though, it could be a breakout year for 3D NAND. Most vendors will begin shipping 64-layer chips, a product that will bring 3D NAND closer to cost parity with planar NAND.

Regardless, fab tool vendors are bullish about 3D NAND. Only 20% of the world’s bit density has been converted from planar to 3D NAND. In other words, the industry is still in the early stages of the technology. “This is a 10-plus year roadmap and we are just at the beginning of it,” said Yang Pan, chief technology officer for the Global Products Group at Lam Research.

200mm surge
A surge in demand for consumer electronics, communications ICs, sensors and other products has created a shortage in 200mm fab capacity.

screen-shot-2016-12-13-at-3-55-19-pm
Fig. 2: 200mm capacity.

It has also created a shortage for 200mm tools. For 200mm, chipmakers tend to buy used tools. In total, there is a demand for over 1,000 used 200mm tools in the market right now, according Emerald Greig, executive vice president for Americas & Europe at SurplusGlobal.

At last count, there are about 1,000 to 1,200 200mm tools in inventory worldwide. But a closer analysis shows that over 50% of those systems are unusable or too old, Greig said. So in reality, there are roughly 500 to 600 usable 200mm tools in inventory now.

“We were hoping for some new available supply at the end of 2016, but that may not come to fruition,” she said. “So, we believe there will be a very large shortage of 200mm tools in 2017. There is steady demand for 300mm tools. Supply is not as much of an issue—yet.”

Related Stories
10nm Versus 7nm
How To Make 3D NAND
Interconnect Challenges Rising
Atomic Layer Etch Heats Up
E-beam Vs. Optical Inspection
Can We Measure Next-Gen FinFETs?
200mm Equipment Shortfall



  • witeken

    “3D NAND is more difficult to make than previously thought, however. Samsung has solved the problems and is shipping 3D NAND. Other vendors are still wrestling with the technology.”

    Micron has already crossed bit parity, and probably cost parity as well.
    http://www.anandtech.com/show/10903/micron-3d-nand-update-2d-and-3d-nand-bit-crossover-gen-2-hits-production

    • Mark LaPedus

      Hi witeken. Thanks for the feedback. I just read the article from the link. I also just read the actual transcript from Ernie Maddock, Micron’s CFO, at the Barclays Technology
      Conference. (Go to Seeking Alpha to see the transcript.)

      Initially, I believe Maddock was talking about Micron’s 32-layer 3D NAND device, which has been shipping for some time. It took Micron some time to develop it, ship it in
      volumes, and get the right yields. It was harder to build than they originally thought. It does, however, have a higher bit density over 2D NAND, enabling it to reach
      the crossover point in bit shipments.

      However, the 32-layer device does not reach price parity over 2D NAND. The real test comes in 2017, when Micron ships a 64-layer device in volumes. This second-generation device is approaching price parity to 2D NAND. Going from 32- to 64-layers isn’t easy. It will take time before Micron brings the product
      into mass production with good yield. All told, 3D NAND is difficult to make. Read
      this article: http://semiengineering.com/how-to-make-3d-nand/

      • witeken

        Not related, but I came across this article from SemiAccurate that was published yesterday but is behind a paywall. It was retweeted a few times, so that made me curious, but the news doesn’t seem to have been published anywhere else. If there’s any chance the information about Cannonlake/10nm can spread to a free site like SemiEngineering, that would be nice.

        http://semiaccurate.com/2016/12/22/intel-10nm-cannon-lake-back/

  • memister

    It would be clearer to use minimum pitch rather than node names to compare costs.