Fabless-Foundry Model Under Stress

By Mark LaPedus
The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond.

Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography.

The sea of change likely will add to the burden on the foundries, which are already under stress as they continue to do more of the R&D and heavy lifting for their customers. At present there is debate about what changes will be needed for this extra load, as well as the looming inflection points on the process and transistor fronts. But the future seems clear in one respect—some changes will be needed.

Intel has taken a big lead in the process race and the foundries are struggling to keep up. In addition, the cost-per-transistor curve has been falling at about 29% per node to enable cheaper systems. At 28nm and 20nm, however, the curve is leveling off at the foundries.

“The fabless companies at the leading-edge, such as Nvidia and Qualcomm, are visibly concerned about their foundries’ ability to keep up with Moore’s Law,” said G. Dan Hutcheson, president of VLSI Research. “To stay in the game, they need a steady decline in cost-per-transistor. If (the curve levels off), this certainly puts into question the common wisdom that the fabless-foundry model is impenetrable.”

The pressure resides squarely on the leading-edge foundries, GlobalFoundries, Samsung, TSMC and UMC, to keep up and deliver. Outside of Intel, vendors face a challenging transition from today’s planar technology at 20nm to finFETs and other architectures at 14nm and beyond.

They also must select between various CMOS technologies to enable scaling. Foundries are leaning towards bulk technology for planar at 20nm and finFETs at 14nm. A rival camp has made a case for silicon-on-insulator (SOI) technology. On the transistor front, there is talk about a hybrid finFET/planar approach. SuVolta has a new planar transistor option. And 3D stacked devices provide yet another avenue.

It’s unclear which technologies will emerge as the winners or losers. What is clear is that only companies with deep pockets can afford to participate. At 22nm, a fab runs $6.7 billion, process R&D is $1.3 billion, and design costs are $150 million, according to GlobalFoundries. And it will cost a staggering $32 billion in total process and tool R&D alone to develop 450mm fabs, according to VLSI Research.

Nonetheless, the fabless-foundry model appears to be far from broken, and predictions about the death of foundries seems greatly exaggerated. The pure-play foundry market is projected to reach $29.6 billion in 2012, up 12% from 2011, according to IHS. This business will grow by 14% in 2013, with double-digit growth continuing in 2014 and 2015, they said.

20nm challenges
Still, the 20nm node represents a pivotal juncture. Intel has made the shift from conventional planar transistors at 32nm to 3D finFETs at 22nm. For foundries, 20nm represents the last node in the planar era, because planar is beginning to suffer from undesirable short-channel effects.

And previously, foundries offered several different process derivatives at a given leading-edge node. But at 20nm, GlobalFoundries, Samsung and TSMC will offer only one leading-edge process. “As we move to 20nm, the fundamental differentiation between high-performance and low-power processes is going away,” explained Mojy Chian, senior vice president of design enablement at GlobalFoundries.

This move, coupled by delays in past nodes, prompted some industry pundits to imply that the fabless-foundry model is somehow broken. Chian dismissed the notion, saying the “fabless-foundry business is thriving.”

So what will keep the fabless-foundry model viable? There must be more collaboration and a new mindset, in which the foundries must change from being mere manufacturing partners into virtual IDMs, Chian said. “New challenges at 20nm and beyond will require deep, IDM-like collaboration to accelerate the time-to-market,” he said.

Vendors must also make some tough choices. On the CMOS front, for example, the foundries will generally move to conventional bulk silicon at 20nm, due to cost. GlobalFoundries is in the bulk camp, but it will also make select chips for IBM and STMicroelectronics using fully depleted SOI (FD-SOI) at 28nm and 20nm.

Regarding SOI, Soitec is offering another CMOS technology option. It provides SOI for planar (FD-2D) and finFET (FD-3D) devices. FD-2D has 241 process steps, compared to 328 for bulk, according to Soitec. SOI wafers are more expensive, but IC makers can offset the costs with fewer process steps, more performance and less power, said Steve Longoria, senior vice president of strategic business development at Soitec.

Jeff Lewis, senior vice president of marketing and business development at SuVolta, said the industry needs a new solution besides bulk and SOI at 20nm. “The cost-per-transistor is higher at 28nm than 40nm/45nm,” Lewis said. “The problems get worse for the 20nm node due to double patterning.”

Another problem is transistor threshold voltage variation, which is caused by systematic and random variations, he said. A phenomenon called random dopant fluctuation (RDF) causes more than 70% of all random variations at 65nm and the problems are getting worse at each node. “In scaling, you start to get mismatches from one transistor to another,” Lewis said. “So the threshold voltages start to vary.”

To solve RDF and other problems, SuVolta recently rolled out a new transistor option that extends conventional bulk CMOS technology. SuVolta’s Deeply Depleted Channel (DDC) technology works by forming a deeply depleted channel when a voltage is applied to the gate.

Beyond 20nm
The problems continue to mount beyond 20nm. It’s unclear if EUV will be ready for the 14nm node. So, IC makers must contend with costly multi-pattering schemes. On the transistor front, Intel has made the migration to finFETs, but its technology has been a hot topic of discussion. Some “have painted Intel as being in trouble with tri-gate because images from a tear-down showed the fin was not squared off, but more shaped like a half-oval,” VLSI’s Hutcheson said.

Others have shown more vertical fins. “It’s very doubtful that Intel is in trouble,” Hutcheson said. “To get a squared off shape would be easy, but it adds steps, hurts yields, and dramatically increases cost.”

Intel may have made some tradeoffs to solve one bulk finFET challenge: height variation. In finFET production, there is an etch step, followed by a back-fill oxide process, and then an implant for junction isolation. The hard part is to make fins with consistent heights during the etch process.

Because of height variability, there are fears that the foundries could struggle making bulk finFETs with any consistency. In response, one foundry claims to have overcome some of these obstacles. According to a paper at the recent IEDM, GlobalFoundries implemented a dual shallow trench isolation (STI) process to ensure fin height control. Its high-k/metal-gate scheme also helped construct “tall/narrow” fins with less doping for better RDF, according to the paper.

FinFETs provide a 40% improvement in power reduction, but the technology still doesn’t put the cost-per-transistor back on the 29% reduction curve. “You are getting a significant power advantage,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “It’s still a challenge to translate that to a die cost reduction.”

All told, the industry should take a harder look at SOI, said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM. “FD-SOI is a fairly simple process, but there is a cost penalty,” Patton said. “When you get to finFETs, it’s a different story. The cost issue becomes neutral between bulk and SOI. Variability is also an advantage for SOI for finFETs.”

In the SOI model, “you place your order to the substrate supplier,” said Horacio Mendez, executive director of the SOI Industry Consortium, a group that promotes SOI. “The height of the fin is pre-determined. It’s pre-made for you.”

Fin variability in bulk finFETs is about 140% to 170% higher, versus SOI finFETs, according to the SOI Consortium. In the front-end-of-the-line (FEOL) process alone, SOI finFETs have 56 process steps, compared to 91 for bulk finFETs, the group said. In total, the FEOL cost for SOI finFETs is $561, compared to $805 for bulk, they said.

Still, GlobalFoundries, TSMC and Samsung are banking on bulk finFETs at 14nm for two reasons. First, it’s unclear if the SOI wafer suppliers can meet demand during crunch times, said GlobalFoundries’ Kengeri. “Historically, customers are not used to designing in SOI. They are comfortable designing with bulk,” he said.

What’s next?
Beside traditional finFETs, there is also talk about a hybrid approach. In this concept, chip makers would combine finFETs and planar devices on the same chip. The planar devices could include analog IP. “This is not easy to do,” Kengeri said. “It’s a complicated process.”

A more likely scenario is that current finFET technology would be scaled at least two generations to 10nm, he said. Then, at 7nm or before, the industry is looking at various next-generation finFETs to solve the mobility problems. The candidates include quantum well finFETs, PMOS germanium finFETs, and SOI. “From a research point of view, we’re looking at everything, but nothing is settled,” Kengeri said.