Faster SerDes For More Efficient Data Centers

The delicate balance of power, performance, and cost in SerDes design.

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The evolving data center presents an imposing set of challenges for system architects as Dennard Scaling fades and Moore’s Law wanes. These include an exponential increase in data, shifting architectural bottlenecks and a never-ending demand for higher performance within the same power and thermal envelopes.

The Internet of Things (IoT), Big Data analytics, in-memory computing and machine learning have resulted in ever-larger amounts of data being generated and analyzed. In many systems today, so much data is transferred across networks that data movement is itself becoming a critical performance bottleneck. Moreover, the very act of moving data is consuming a significant amount of power, so much so that it’s often more efficient to move the computation to the data instead.

The industry is currently pursuing a number of techniques to bolster performance and improve power efficiency, including acceleration with FPGAs and other silicon, as well as Near Data Processing to minimize data movement and energy consumption. Concurrently, data centers routinely upgrade critical infrastructure, replacing older silicon with newer processors and memory that are often equipped with a faster network interfaces utilizing SerDes (Serializer/Deserializer) technology. As SerDes speeds hit 56Gbps and beyond, engineers are grappling with a number of issues, including rising design costs, maintaining good signal integrity by reducing susceptibility to noise and jitter, supporting backwards compatibility for legacy standards and minding the power-performance ratio.

Optimizing performance at the lowest possible power draw and smallest silicon area is one way to successfully design and differentiate high-speed SerDes at 56Gbps and beyond. Decisions about architecture, circuits, package and board design, and operating environment will be more critical than ever before moving forward and will influence not only the design space that the serial interface can operate in, but also the cost, power, and performance as well.

The need to support backwards compatibility will heavily influence 56Gbps SerDes designs as well. Eliminating unnecessary features and legacy standards will also be beneficial, but will come at the cost of reducing the number of potential customer applications. The delicate balance between supporting a larger number of standards and a wider range of operation, which requires new features and capabilities like advanced equalization at high end data rates while minimizing impact at lower data rates, will become more precarious in the future.

Working closely with customers and partners will remain the most critical part of the SerDes design process. A collaborative approach will help ensure first-time-right silicon and accelerate time-to-market. Co-design efforts that utilize advanced modeling capabilities and common tools will grow in importance for successfully designing high speed silicon, packages, and channels.  SerDes designs will need to integrate ever increasing amounts of on-chip monitoring and testing capabilities, accommodate specific requirements for package and board designs, and understand the range of routing requirements in order to correctly implement future demanding, high-speed designs.

Achieving higher data rates while balancing power, performance, and cost requirements for high-speed serial links may very well be the most difficult aspect of designing future SerDes cells. Providing this balance will grow ever more important as the industry moves forward, and while this will challenge future SerDes designers, it will also be key to differentiating high-speed SerDes at 56Gbps and beyond for applications such as power efficient data centers and servers.