Field Solvers To The Rescue

By Pallab Chatterjee

Field solvers have always been part of the Parasitic Extraction (PEX) world, but due to their long run times and complexity in configuration, their role was relegated to the setup/reference table generation for the pattern based 1-D and 2-D RC extraction tools. That’s about to change.

Mentor, in combination with STMicroelectronics, one of it customers, said that at 22nm field solvers are the required method of determining the PEX values with full live data. This acknowledgment follows Silicon Frontline’s claim that the necessity for the new technology is mandatory starting at the 32nm process node due to process complexity.

For process technologies from 2 microns through the 65nm technology node, PEX has been utilizing full 3D Maxwell’s Equations electric field solvers to help determine the R and C values for static conditions that are the technology tables used by all extractors. Based on the industry-leading and reference product Raphael (TMA to Avanti to Synopsys), the accuracy for determining what the extracted values should be has been set by the text description of the vertical process topology (layer stacking and inter-layer dielectrics) used to drive the PEX tools.

The field solver is used to create the vertical and coupling capacitance values between the interconnect layers with respect to substrate and to adjacent interconnects. Because these values change with spacing and with how many layers appear at a time (for example, M2 over substrate vs. M2 under M3 + over M1 over well over substrate), the generation of the reference tables for a process could literally takes days for all the computations to finish.  The results are a complex table of drawn patterns that the PEX tools searches for in the layout, and when it finds one it determines the size and factors that with the values in the reference table.

At 32nm and below this method is no longer sufficient, however. The technology that is used to make the 11-15 interconnect layer processes now has enormous variability in layer thickness (both interconnect layer and inter-layer dielectric). There also are differences in the profiles in terms of the size and shape of single vs. multiple vias, as well as changes in the via profiles per layer. And just to make things even more complicated, there are multiple materials used for contacts and vias by context (gate poly contacts vs. field poly contacts, for example.) As a result, it is no longer possible to create a static reference table of characteristics for “look up” by the PEX tool.

The PEX environment must now operate in true 3D mode—instead of 1D of look down or 2D of look down and to the side—with full process flow information, to determine dynamically what the R’s and C’s should be for a given net, in all conditions and patterns of the net.

Silvaco introduced its Clever product nearly 10 years ago to address this issue at the IP/gate level. It is a full multi-threaded, multi-core-aware 3D field solver that has been used to address these issues for critical design in image sensors, memories, and other highly capacitance sensitive structures since the 1 micron arena. The product has been used mostly by integrated device manufacturers (IDMs) and fabs, due to the close reliance on having access to the process flow information that is needed to drive the tool, as well as the reluctance by the fabs to release that level of information to most end customers.

In the new scenario, Silicon Frontline, Mentor (and most likely Synopsys in the near future), will work with foundries and IDMs to get the appropriate process and modeling information and secure it in the tool, so the information is both available and unreadable by people.  This new cooperation was driven by the necessity of the process technology, not any inherent new-found trust with the EDA vendors, to be able to have SOC and IP designers create functional parts.

The Silicon Frontline product has been commercially available since mid 2009. Mentor’s tool will be named and available soon. And most of the customers are assuming the Synopsys offering will be announced sometime this year. These products have applicability at larger geometry processes using chip-to-chip stacked die, as there is significant coupling from the thinned and “potato-chip profile” top chip that is connected to through-silicon vias or other bonds.