First Look: 5nm

Initial test chips are out the door, but there’s a lot more work and uncertainty ahead.

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By the time the 5nm semiconductor manufacturing process node reaches mass production readiness, the hurdles and challenges will no longer be open for discussion. But as of this moment, some of them seem almost insurmountable, raising new questions about the continued viability of Moore’s Law.

There has been much written about the end of Moore’s Law for nearly two decades. Even the mainstream press has begun jumping on the bandwagon recently, discussing the free ride the semiconductor and electronics industry have had over the past five decade due to classical scaling. Historically, as features were shrunk, performance increased, leakage current dropped, and costs went down. That free ride ended at 130nm, and each new node since then has been a struggle of increasing magnitude on all sides, starting with the need for different gate oxides and interconnect materials and more sophisticated EDA tools to process far more data.

“The way I look at it, we stopped being ingenious at some point and became more about pushing tools and flows when we started to use the EDA solutions more as an enabling point and not as more of a means to an end — and not the actual process itself,” said Aveek Sarkar, vice president of product engineering and support at Ansys-Apache. “As we go down into these technology nodes, some of these concepts – like device physics, and worrying about what is going about inside the standard cells and from an SoC point of view — all of a sudden will become very important.”

That also means the entire supply chain, from initial architecture to the back end of line in manufacturing, will have to work much harder and much more collaboratively. Getting working silicon with reasonable yields is no longer guaranteed, particularly when the manufacturing processes themselves take more time to firm up and IP and tools need to be created long before version 1.0 of the next process is ready.

“Traditionally, if you look at 65 nm/40 nm/28nm for SoC designers, the standard cell was somebody else’s problem, Sarkar said. “‘Let’s just design gate up. Let’s meet our timing constraints. Let’s meet power to an extent.’ But now, we’re talking about the reliability of the finFET. How much heat is generated, how densely all these gates are placed together, is pretty much becoming a bottleneck in design.”

As such, design for reliability will be the key driver going forward, he said. “When we talk about low-power, we focus on power for a multitude of reasons. All these years it was, ‘Can we improve battery life? Can we cram more functionality into this iPhone form factor without blowing up the size of the battery?’ But now people are realizing there is a certain point of diminishing returns. And battery technologies are also improving.”

There is a growing realization that it’s not just important to reduce power for the sake of battery life. In many cases it’s a question of whether these devices will work and be manufactured reliably enough. “We can make a very big clock buffer, but it’s probably going to burn out either itself or its neighboring parts—or it will switch so much current that the 500 mV supply rail will collapse. So for low power design, the focus will shift towards driving more reliable electronics and less noise on the chip, because the less power you consume, the less noise you have on the chip as well,” Sarkar said.

5nm test chip
The first 5nm test chip was rolled out by IMEC and Cadence last month using a combination of EUV, 193nm immersion Lithography and self-aligned quadruple patterning (SAQP).

Praveen Raghavan, principal engineer at Imec, explained that the basic work here provided an understanding of patterning on the back end layers. “This is on the first routing layers, which means metal2, vias and metal3. It’s a pure understanding of where the limits are in terms of lithography, where the limits are in terms of etch, also in terms of all the secondary design rules. That was a key part of the work.”

Commercial production of 5nm is still quite far out. It remains unclear what exactly the pitch will be, so in the test chip a mix of pitches was used — from 36nm pitch, all the way down to 24nm, which is close to the theoretical limit of quadruple patterning. In theory it is possible to go down to 20nm pitch, but with some margin 24nm is more likely.

The test chip is composed of three sets in order to do a mix and match scenario with the lithography. The first scenario was a pure scenario. The lines, vias and metal3 were all printed with EUV. All of this was uni-directional, given the 24nm pitch.

In the second scenario, metal2, metal3 and the mesh of the metal was printed with SAQP. Then the cuts in the metal were printed with a single exposure of EUV, and the vias were single exposure EUV. The same scenario was used on metal3, as well.

In the third scenario, which was a pure 193i scenario, the cuts in the blocks and the vias were decomposed into three colors.

Rainbow effect
One of the important takeaways from the test chip, Raghavan explained, is that if 193i is taken as the only primary option, the pitches can be pushed down to 24nm, but the number of colors needed for the block mask or the via mask is going to be astoundingly high.

“It might look like five colors or six colors, which is in theory, for mass production, not viable. If you take all the margins for etch placement error and process variation on all five colors, this will be phenomenally hard. There are certain layers, like the vias and the blocks, which for EUV makes immediate sense.”

He believes that for the lines 193i, will be the first choice. “EUV has certain advantages certainly in the sense that you don’t need to create a full mesh of lines but you can try to print exactly what you want. That means you would have a reduced capacitance penalty because you don’t have all the dumps next to each other. That has certain advantages, but it all depends on which pitches one might come out in 5nm, and if the pain is high enough to switch over to EUV.”

Timeline?
But how long will it take for more of these issues to get worked out? Raghavan stressed it is tough to speculate. “The resist needs a breakthrough. Source is improving. One of the good things we were all hoping EUV would bring is being able to maintain 2D styles in standard cells. If EUV was to come early, people can live with 2D styles as they do today. If EUV doesn’t come in time, and people have to switch to uni-directional routing using 193i, EUV will be pushed out even more in the sense that people have already done the 1D, so people would want to push 1D to the limit and maximize their investment. In that sense, EUV gets bigger breathing room if you look at it in a positive way. But in a negative way, indeed it is pushed out even more. And that’s just on the metal layers. The layers where we have not yet seen a breakthrough is in the layers like vias and block masks, because they are truly random.”

Lithography is only part of this incredibly complex picture, though. Tools need to be developed to automate tasks and manage the huge amount of data. Vassilios Gerousis, distinguished engineer at Cadence, said that one of the big breakthroughs at 5nm is just being able to do lines and cuts. “Doing that in the router is very new technology,” he said. “Not just that, but the ability of it to choose colors for those metal cuts. That was also a breakthrough for us in terms of place and route technology.”

No matter which way things go, EUV, 193i, or some combination of different technologies that could include hybrid deposition, the tools will be ready. But it will be more difficult, from one end to the other.

“If you look at the lines, they are very close to each other,” said Gerousis. “That means coupling is increased, and that also means power is increased. There is technology we’re working on with Imec to use lithography with certain cuts, but the EUV will definitely help in this area because you don’t need every track to be filled. In that regard, the power is really important, and that’s leading such activities to help select a better lithography option.”

Raghavan explained that one of the challenges when working at such tight pitches is that very narrow spaces within the metal lines would be required, something that is particularly difficult in conjunction with low-k integration. “That means actually that even if you try to do low-k there will be quite a bit of sidewall damage, which means the effective capacitance will have to be even higher. So you might not be able to have the whole space with low-k but rather, a part with low-k and a part which is damaged. In that sense it would be really nice if EUV can be pulled in to actually make sure that we do not have all of these dummies.”

Money talks
One question that is being asked more frequently across the semiconductor industry is how many companies in the world will be able to afford the investment in 5nm. In fact, a long-running joke is that the number of customers will match the process node number.

“Many people say the end is near, but the reality we see is that the end is not near,” Gerousis said. “We see creativity coming in and innovation coming in. That will continue to evolve. People who always will look for technology innovation have a few customers that can invest. Also, from the foundry perspective there are main foundries that will continue to invest because that’s their bread and butter. For customers, the most advanced customers will continue to push in this area – primarily because they need to stay competitive, although the numbers will be fewer than usual going from one node to the next node.”

Raghavan agreed it all boils down to the economics. “If you look at it from the point of view of what has happened with even in 193i, people have gotten a lot more creative purely because it’s not just the lithography that eventually determines the cost – it’s also in the complete process integration and in the design part. All the secondary, tertiary and even the fourth-order rules, those are also places where people start to play with to ensure that you can get the maximum buck out of the design. Restated another way, while costs indeed will go up, what also drives people is that they want to do the most for the cost they invested. In that sense, scaling might just accelerate rather than decelerate.”

But over what time period? “It might happen that nodes come out later ,but they might get more aggressive on things to make sure that because you have made the premium investment, you want to get the most out of it. So once you do the investment, you might want to push it all the way down because that goes to the maximum economic benefit,” he asserted.

Still, getting to 5nm requires resolving some immediate technical issues, namely, device design, Raghavan continued.

“Even more than lithography, device design is going to be a very big challenge, and the reason is that getting any more current out of the device is getting to be phenomenally more difficult,” he said. “That means your typical 20% performance boost node to node is something that one would have to give up. The reason for this is that even if you have a perfect device — forget all the variability and the lithography and all of these aspects — fundamentally you are dealing with a very, very few number of atoms, so all of your resistances are very much quantum defined. Going small only make things worse. Physics is against you here. There’s a lot of talk about high mobility materials, but change in materials is something that is one of the most un-preferred options in a fab. People will try to push it off until the last moment. High mobility materials also come with the downside in that you do not have the full spectrum of Vt. You would have a high amount of leakage, so co-integration is needed with another material (such as silicon). Co-integration then becomes a problem because III-V co-integration with silicon is a whole different ballgame.”

So by the year 2020 or 2021 will 5nm be ready for mass production, as per the ITRS roadmap? Given the creativity and innovation in this industry, it wouldn’t be surprising. But there also are a lot of other options under development, from 2.5D and 3D stacked die and FD-SOI at higher nodes, that should provide some interesting price, performance and power comparisons.



  • memister

    Via patterning should be self-aligned rather than direct exposure. That should relieve the density burden.

  • GP

    IMEC has a surprisingly limited approach to 5 nm. Other places are already considering cut-less approaches.

  • Israel Beinglass

    One issue that people are not discussing is how to change the interconnect module. For over 15 years we are with the same module/materials Ta/TaN/Cu. we need some new ideas and new materials.