Formal Verification For Post-Silicon Debug

How to identify bugs earlier when the cost of fixing them is much lower.


Bug escape costs grow considerably with each and every subsequent step in the design flow, to the point of being exorbitantly high once at the silicon level. As a result, these high costs of bug escape are driving customers to embrace formal verification for post-silicon debug and to begin using formal far earlier in the flow for their next design projects. The Cadence JasperGold Verification System’s ability to quickly identify bugs, assure the cleanliness of sub-blocks, and verify the completeness of design fixes makes it the highest value post-silicon debug tool in the team’s arsenal.

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