Hybrid Memory Cube – Ready For Prime Time

With the release this week of Hybrid Memory Cube (HMC) 2.0, designers can get their hands on mature, standards-based IP that can be used to significantly scale the performance of servers and data centers. HMC offers bandwidths up to 320 GB/s – 12X that of standard memory solutions like DDR4 – while consuming significantly less power. These benefits are too significant to ignore for ASIC, SoC and ASSP designers developing solutions for next-generation networking, high-performance computing (HPC), test equipment, and storage products.

It’s no secret that traditional DDR solutions are running out of steam. Take the example of a packet buffer in a 400G network application. Delivering the necessary memory bandwidth would require the use of 70 x16 DDR4 memories, each operating at 2400 Mb/s. Contrast that with an HMC solution, where a dual HMC link operating at 25 Gb/s can be used, significantly reducing system-level power and board real estate. How is this possible? HMC uses a revolutionary architecture, vertically stacking DRAM die on top of logic using 3D interconnects.

More Bandwidth and Performance
Compared to HMC 1.0, the new HMC 2.0 specification doubles the maximum link speed to 30Gbps and corresponding link aggregate bandwidth to 480 GB/s (3.84 Tb/s).

The updated specification also provides designers with even more memory performance. First, the number of vaults has been doubled to 32. Vaults are vertical stacks of memory die with corresponding memory controllers. Because each vault operates independently, there is a high-level of parallelism.

HMC uses a packet-based protocol, supporting packet sizes of 16, 32, 48, 64, 80, 96, 112 and 128 bytes. The new version of the specification adds support for 256 byte packets there by increasing efficiency of data transfers.

HMC 2.0 also features significantly enhanced support for atomic commands. Atomic commands involve reading 16 bytes of data from the memory, performing an operation (as defined by the command) and writing the results back to the same memory location. By executing the memory-intensive operation near the memory, the HMC protocol reduces the amount of data that must be transferred back and forth between the memory and the host. HMC 2.0 has added a large number of atomic commands that now support arithmetic, bitwise, Boolean and comparison operations.

The HMC Controller
The HMC specification was co-developed by Altera, ARM, IBM, Micron, Open-Silicon, Samsung, SK Hynix and Xilinx. Open-Silicon has taken a lead role in delivering the controller piece of the HMC solution – the critical piece of IP that ensures seamless communication between memory and user logic. The controller includes the transaction, link, and non-SerDes portion of the physical layer.

Beyond simply meeting the standard’s requirements, the controller must provide designers with flexibility in terms of customization, as this can directly impact the differentiation they deliver in their products. A highly configurable controller solution enables designers to choose from a number of data path widths and user interface options, allowing for a quick tradeoff between performance, latency and power.

Together, the HMC controller and PHY provide a breakthrough memory solution that should deliver the bandwidth required by high-performance systems for years to come.

For more information on Open-Silicon HMC solutions, click here.