Improving Emulation Throughput For Multi-Project SoC Designs

Methods for boosting design team productivity for multiple complex SoC designs.

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As design sizes grow, so, too, does the verification effort. Indeed, verification has become the biggest challenge in SoC development, representing a majority share of the development cost, both for hardware itself and for verification at the hardware/software interface. And today, it’s not uncommon for companies to have distributed teams working on multiple SoC designs in parallel. In some cases, teams have been known to share emulation resources amongst tens of projects. In this paper, we’ll discuss the characteristics you should look for to boost your emulation throughput and design team productivity in order to effectively and efficiently manage the delivery and performance targets for multiple, complex SoC designs.

To read more, click http://www.cadence.com/rl/Resources/white_papers/emulation_throughput_wp.pdf?CMP=102615_PreLaunch_bb.